公开(公告)号：US20160300614A1

公开(公告)日：2016-10-13

申请号：US14392273

申请日：2014-06-17

Applicant: NEC CORPORATION

Inventor： Ryusuke NEBASHI ,  Noboru SAKIMURA ,  Tadahiko SUGIBAYSHI

IPC: G11C15/02

CPC classification number: G11C15/02 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C15/046

Abstract: In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data.

Abstract translation: 为了提供减少内容可寻址存储单元的面积并抑制计算相似度的内容可寻址存储器中的泄漏电流的技术，本发明的内容可寻址存储单元包括：电阻网络，其包括多个电流路径 ，用于响应于输入数据选择电流路径的逻辑电路，以及可变电阻型非易失性存储元件，其设置在至少一个电流路径上，并存储数据，并且其电阻值根据 基于输入数据和存储数据的逻辑计算; 以及与电阻网络和匹配线连接的充电/放电电路，其根据输入数据和存储的逻辑计算结果改变从输入信号到匹配线直到输出信号的延迟时间 数据。