公开(公告)号：US12124848B2

公开(公告)日：2024-10-22

申请号：US17277532

申请日：2019-08-21

Applicant: NEC Corporation

Inventor： Kento Iwakawa

IPC: G06F9/30 ,  G06F8/41

CPC classification number: G06F9/30036 ,  G06F8/4441 ,  G06F9/30018 ,  G06F9/30065 ,  G06F9/30101

Abstract: An information processing apparatus according to the present invention includes: a load instruction generating unit configured to generate an instruction to continuously access a memory in which a real part and an imaginary part composing complex data are alternately arranged, in accordance with arrangement of the real part and the imaginary part, and load the real part and the imaginary part as respective elements of a vector register; and an operation instruction generating unit configured to generate a vector operation instruction including an instruction to perform a vector operation of elements corresponding to element numbers different from each other between two vector registers and an instruction to perform a masked vector operation.