公开(公告)号：US11818254B2

公开(公告)日：2023-11-14

申请号：US16639000

申请日：2018-08-16

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi ,  Ryo Kikuchi ,  Koji Chida

IPC: H04L9/08 ,  G09C1/04 ,  H04L9/00

CPC classification number: H04L9/085 ,  G09C1/04 ,  H04L9/008 ,  H04L9/0861 ,  H04L2209/46

Abstract: A share [x]i of plaintext x in accordance with Shamir's secret sharing scheme is expressed by N shares [x0]i, . . . , [xN−1]i, and each share generating device Ai obtains a function value ri=Pm(i(−))(si) of a seed si, obtains a first calculated value ζi=λ(i, i(−))[xi(−)]i+ri using a Lagrange coefficient λ(i, i(−)), a share [xi(−)]i, and the function value ri, and outputs the first calculated value ζi to a share generating device Ai(−). Each share generating device Ai accepts a second calculated value ζi(+), obtains a third calculated value zi=λ(i, i(+))[xi]i+ζi(+) using a Lagrange coefficient λ(i, i(+)), a share [xi]i, and the second calculated value ζi(+), and obtains information containing the seed si and the third calculated value zi as a share SSi of the plaintext x in secret sharing and outputs the share SSi.

公开(公告)号：US11797540B2

公开(公告)日：2023-10-24

申请号：US17252290

申请日：2019-06-13

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi ,  Koki Hamada

IPC: G06F16/2455 ,  G06F21/62

CPC classification number: G06F16/2456 ,  G06F21/6254

Abstract: A secure joining system is a secure joining system comprising a plurality of secure computation apparatuses; and the plurality of secure computation apparatuses are provided with vector joining parts 11n, first permutation calculating parts 12n, first permutation applying parts 13n, first vector generating parts 14n, second vector generating parts 15n, bit-flipping parts 16n, second permutation calculating parts 17n, second permutation applying parts 18n, third vector generating parts 19n, inverse permutation applying parts 110n, vector separating parts 111n, third permutation applying parts 112n, attribute value permutating parts 113n and fourth vector generating parts 114n.

公开(公告)号：US11515998B2

公开(公告)日：2022-11-29

申请号：US16638987

申请日：2018-08-16

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi ,  Ryo Kikuchi

IPC: A61C9/00 ,  H04L9/06

Abstract: A secure computation device obtains concealed information {M(i0, . . . , iS−1)} of a table M(i0, . . . , iS−1) having one-variable function values as its members. It is to be noted that M(ib, 0, . . . , ib, S−1) generated by substituting counter values ib, 0, . . . , ib, S−1 into the table M(i0, . . . , iS−1) represents a matrix Mb, γ, μ, which is any one of Mb, 2, 1, . . . , Mb, 3, 2. The secure computation device obtains concealed information {Mb, γ, μ} by secure computation using concealed information {ib, 0}, . . . , {ib, S−1} and the concealed information {M(i0, . . . , iS−1)}, and obtains concealed information {Mb, Γ, MU} of a matrix Mb, Γ, MU, which is obtained by execution of a remaining process including those processes among a process Pj, 1, a process Pj, 2, a process Pj, 3, and a process Pj, 4, that are performed subsequent to a process Pγ, μ.

公开(公告)号：US11329808B2

公开(公告)日：2022-05-10

申请号：US16970552

申请日：2019-02-14

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi ,  Gembu Morohashi ,  Koji Chida

IPC: H04L9/08 ,  H04L9/32

Abstract: A secure computation device obtains a first concealed verification value [z]i=[w−ω]i with secure computation by using concealed authentication information [w]i which is preliminarily stored and concealed authentication information [ω]i which is inputted, obtains a concealed extension field random number [rm]i∈[Fε] which is a secret sharing value of an extension field random number rm, obtains a second concealed verification value [ym]i in which ym is concealed with secure computation by using the first concealed verification value [z]i, and obtains a third concealed verification value [rmym]i with secure computation by using the concealed extension field random number [rm]i and the second concealed verification value [ym]i and outputs the third concealed verification value [rmym]i.

公开(公告)号：US11316674B2

公开(公告)日：2022-04-26

申请号：US17049340

申请日：2019-04-22

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi ,  Koki Hamada

IPC: H04L29/06 ,  H04L9/08 ,  G09C1/00

Abstract: An aggregate median is efficiently obtained while confidentiality is kept. An order computing part generates ascending order a and descending order d within a group when a table which has been stably sorted based on a desired value attribute and a key attribute is grouped based on the key attribute. A subtracting part generates shares {a-d}, {d-a} of a-d, d-a. A bit deleting part generates shares {a′}, {d′} of a′, d′ obtained by excluding least significant bits from {a-d}, {d-a}. An equality determining part generates shares {a″}, {d″} of {a″}:={|a′=0|}, {d″}:={|d′=0|}. A format converting part (15) converts {a″}, {d″} into [a″], [d″]. A flag applying part generates shares [va], [vd] of [va]:=[v1a″], [vd]:=[v1d″]. A permutation generating part generates shares {{σa}}, {{σd}} of permutations σa, σd which sort ¬a″, ¬d″. A median computing part generates a share [x] of a vector x.

公开(公告)号：US11099984B2

公开(公告)日：2021-08-24

申请号：US16652113

申请日：2018-10-02

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi

IPC: G06F12/0802 ,  G06F12/109

Abstract: To perform permutation processing at high speed. A number-of-elements determination unit (22) calculates the number of elements to be contained in each allocation destination. A start position determination unit (23) calculates a start position corresponding to each allocation destination. An allocation destination determination unit (24) calculates a sequence of values representing allocation destinations in a buffer. A permutation generating unit (25) calculates a sequence of values representing permutation destinations within the respective allocation destination. An initial position setting unit (31) sets the start position into a value indicating a position within processing corresponding to each allocation destination. A rearrangement unit (32) sets the elements of a vector into the respective allocation destinations in the buffer. A permutation execution unit (33) generates an output vector by executing an arbitrary inverse permutation algorithm on the respective allocation destinations.

公开(公告)号：US10929502B2

公开(公告)日：2021-02-23

申请号：US15571156

申请日：2016-05-11

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi

IPC: G06F17/16 ,  G06F7/72

Abstract: In a process of taking a first square matrix formed from elements of a finite field as input and obtaining at least some of entries of a second square matrix which includes an upper triangular portion resulting from triangulation of the first square matrix, product-sum operation is performed on entries as operands at multiple positions in a matrix which is based on the first square matrix to obtain a product-sum operation result corresponding to an entry at a different position than the operands, and reduction of the product-sum operation result is performed.

公开(公告)号：US10885814B2

公开(公告)日：2021-01-05

申请号：US15557585

申请日：2016-02-01

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi ,  Koji Chida ,  Ryo Kikuchi ,  Koki Hamada

IPC: H04L29/06 ,  G09C1/00

Abstract: An efficient share recovery technique for Shamir's secret sharing is provided. n share recovery apparatuses p0, . . . , pn−1 generate a share [r]i of a secretly shared value shared through Shamir's secret sharing, which becomes a random number r when restored. k share recovery apparatuses σ0, . . . , σk−1 calculate a share [b]i by subtracting the share [r]i from a share [a]i. The share recovery apparatus τk receives the shares [b]0, . . . , [b]k−1 from the share recovery apparatuses σ0, . . . , σk−1. The share recovery apparatus τk recovers shares [b]k, . . . , [b]k+m−1 using the shares [b]0, . . . , [b]k−1. m−1 share recovery apparatuses τk+1, . . . , τk+m−1 receive a share [b]j from the share recovery apparatus τk. m share recovery apparatuses τk, . . . , τk+m−1 calculate the share [a]j by adding the share [r]j to the share [b]j.

公开(公告)号：US10509630B2

公开(公告)日：2019-12-17

申请号：US15541417

申请日：2016-01-13

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi

IPC: G06F7/58 ,  G09C1/00 ,  G06F7/72

Abstract: A random number acquiring unit 15 obtains a first sequence that comprises values of digits of a random number represented by a binary number as elements. A logical product arithmetic unit 16 obtains a third sequence that is results of elementwise logical product operation between the first sequence and a second sequence that comprises values of digits of one or more Mersenne numbers represented by one or more binary numbers and a zero value as elements.

公开(公告)号：US10348491B2

公开(公告)日：2019-07-09

申请号：US15569187

申请日：2016-05-11

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Dai Ikarashi

IPC: H04L9/08 ,  G09C1/00

Abstract: Computational complexity is reduced in accordance with given k and n. A random number generation unit 12 generates random numbers r0 to rk−2 ϵGF(xq). A share generation unit 14 generates shares b0 to bn−1 by calculating a product of a vector a=(r0, . . . , rk−2, s), having the random numbers r0 to rk−2 and plaintext s ϵGF(xq) as its elements, and a matrix A. A share selection unit 15 generates a vector b′=(bp0, . . . , bpk−1) having, as its elements, k shares bp0 to bpk−1 selected from the shares b0 to bn−1. An inverse-matrix generation unit 16 generates an inverse matrix A′−1 of a k-degree square matrix having the p0-th to pk−1-th rows of the matrix A. A plaintext calculation unit 17 restores the plaintext s by multiplying the k-th row of the inverse matrix A′−1 and the vector b′.