公开(公告)号：US20210184689A1

公开(公告)日：2021-06-17

申请号：US17257315

申请日：2018-12-13

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION

发明人： Jie PU ,  Gangyi HU ,  Dongbing FU ,  Zhengping ZHANG ,  Liang LI ,  Ting LI ,  Daiguo XU ,  Mingyuan XU ,  Xiaofeng SHEN ,  Xianjie WAN ,  Youhua WANG

IPC分类号： H03M1/12 ,  G06F1/10 ,  H03M1/06

摘要： The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

公开(公告)号：US20210135678A1

公开(公告)日：2021-05-06

申请号：US17257011

申请日：2018-07-25

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION

发明人： Jie PU ,  Gangyi HU ,  Jian'an WANG ,  Guangbing CHEN ,  Liang LI ,  Ting LI ,  Daiguo XU ,  Xingfa HUANG ,  Xi CHEN ,  Tiehu LI ,  Youhua WANG

IPC分类号： H03M1/06

摘要： The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.

公开(公告)号：US20180358976A1

公开(公告)日：2018-12-13

申请号：US15742835

申请日：2015-08-20

申请人： NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION

发明人： Jie PU ,  Gangyi HU ,  Xiaofeng SHEN ,  Xueliang XU ,  Dongbing FU ,  Ruitao ZHANG ,  Youhua WANG ,  Yuxin WANG ,  Guangbing CHEN ,  Ruzhang LI

IPC分类号： H03M1/06

CPC分类号： H03M1/0609 ,  H03M1/10

摘要： A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimation correction.