公开(公告)号：US20240178948A1

公开(公告)日：2024-05-30

申请号：US18528175

申请日：2023-12-04

Applicant: Nokia Solutions and Networks Oy

Inventor： Yi Zhang ,  Deshan Miao ,  Jingyuan Sun ,  Keeth Saliya Jayasinghe

IPC: H04L1/1867 ,  H04L1/00 ,  H04L5/00

CPC classification number: H04L1/1896 ,  H04L1/0005 ,  H04L5/0055

Abstract: There is provided a method comprising determining a number of acknowledgment bits allocated to at least one transmit block, the at least one transmit block comprising a plurality of code blocks, allocating each of the plurality of code blocks to a respective code block group, based on the number of acknowledgment bits allocated to the at least one transmit block and the number of the plurality of code blocks, wherein each code block group is associated with one of the number of acknowledgment bits and causing transmission of the acknowledgment bit associated with each respective code block group based on a determined acknowledgement result for the respective code block group.

公开(公告)号：US11558148B2

公开(公告)日：2023-01-17

申请号：US17345297

申请日：2021-06-11

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Keeth Saliya Jayasinghe Laddu ,  Yi Zhang ,  Jingyuan Sun

IPC: H03M13/00 ,  H04L1/00 ,  H03M13/11

Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

公开(公告)号：US11070314B2

公开(公告)日：2021-07-20

申请号：US16637118

申请日：2017-08-18

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Keeth Saliya Jayasinghe Laddu ,  Yi Zhang ,  Jingyuan Sun

IPC: H03M13/00 ,  H04L1/00 ,  H03M13/11

Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.