公开(公告)号：US20140010276A1

公开(公告)日：2014-01-09

申请号：US13935868

申请日：2013-07-05

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chia-Hao HSU ,  Yu-Hsing CHIANG

IPC: H04L25/03

CPC classification number: H04L25/03949 ,  H04L7/0338 ,  H04L25/03006

Abstract: A clock data recovery circuit includes an equalizer, a multi-phase clock generator, a sampling and check unit, a signal edge detection unit and an adjusting unit. The equalizer performs an equalization on an incoming data signal. The multi-phase clock generator generates multiple clock signals and at least one pair of check signals. The sampling and check unit samples the incoming data signal according to the clock signals to obtain a sequence, and checks whether the sequence matches a predetermined pattern. If so, the signal edge detection unit controls the sampling and check unit to detect a transition between values of the sequence two on two based on the pair of check signals to obtain a detection value. The adjusting unit determines whether the transition is too early or too late according to the detection value, and adjusts the equalization on the incoming data signal according to the determination result.

Abstract translation: 时钟数据恢复电路包括均衡器，多相时钟发生器，采样和检查单元，信号边缘检测单元和调整单元。 均衡器对输入数据信号执行均衡。 多相时钟发生器产生多个时钟信号和至少一对校验信号。 采样和检查单元根据时钟信号对输入数据信号进行采样，以获得序列，并检查序列是否匹配预定模式。 如果是，则信号边缘检测单元控制采样和检查单元，以基于一对检查信号来检测序列二的值之间的转换，以获得检测值。 调整单元根据检测值确定转换是否太早或太晚，并且根据确定结果调整输入数据信号上的均衡。