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公开(公告)号：US10038545B1
公开(公告)日：2018-07-31
申请号：US15660397
申请日：2017-07-26
申请人： Xilinx, Inc.
发明人： Zhaoyin D. Wu , Winson Lin , Yu Xu , Geoffrey Zhang
CPC分类号： H04L7/0025 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0004 , H04L7/0012 , H04L7/033 , H04L7/0334 , H04L7/0337 , H04L7/0338 , H04L43/028 , H04L43/16
摘要： A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.
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公开(公告)号：US09966994B2
公开(公告)日：2018-05-08
申请号：US15098031
申请日：2016-04-13
CPC分类号： H04B3/462 , H04L1/00 , H04L7/0338 , H04L7/10 , H04L43/022
摘要： Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.
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公开(公告)号：US20170310327A1
公开(公告)日：2017-10-26
申请号：US15264574
申请日：2016-09-13
发明人： Yen-Chung CHEN , Wen-Juh KANG , Chen-Yang PAN
CPC分类号： H03L7/0807 , H03K19/21 , H03K21/38 , H03L7/091 , H03L7/093 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0338
摘要： A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.
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4.发明申请公开(公告)号：US20170214515A1
公开(公告)日：2017-07-27
申请号：US15369806
申请日：2016-12-05
申请人： Rambus Inc.
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
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公开(公告)号：US09705665B2
公开(公告)日：2017-07-11
申请号：US15009696
申请日：2016-01-28
发明人： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC分类号： H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
摘要： A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
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公开(公告)号：US09602085B2
公开(公告)日：2017-03-21
申请号：US14894323
申请日：2013-11-07
申请人： Synopsys, Inc.
IPC分类号： H03K3/00 , H03K3/037 , G06F1/12 , H04L7/033 , H03K3/3562
CPC分类号： H03K3/0375 , G06F1/12 , H03K3/35625 , H04L7/0338
摘要： A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1 , DOUT2) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUT1 , DOUT2) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.
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公开(公告)号：US20160149695A1
公开(公告)日：2016-05-26
申请号：US15009696
申请日：2016-01-28
发明人： Abhishek CHOWDHARY , Vivek UPPAL , Alok KAUSHIK , Sajal Kumar MANDAL , Tapas NANDY , Sanjeev CHOPRA
CPC分类号： H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
摘要： A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
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8.发明申请System and Apparatus for Clock Retiming with Catch-Up Mode and Associated Methods 有权用于具有追赶模式和相关方法的时钟重新定时的系统和装置公开(公告)号：US20160119111A1
公开(公告)日：2016-04-28
申请号：US14523599
申请日：2014-10-24
发明人： Kenneth W. Fernald , Imranul Islam
IPC分类号： H04L7/00
CPC分类号： H04L7/0016 , H04L7/0338
摘要： An apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal.
摘要翻译： 一种装置包括响应于第一信号操作的模拟或混合信号电路，以及响应于第二信号操作的数字电路。 该装置还包括信号重新定时电路。 信号重新定时电路重置数字信号源的输出信号，以通过对数字信号源的输出信号的边沿进行重新定时以降低第一信号的周期边界来减小数字电路与模拟或混合信号电路之间的干扰。
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9.发明申请公开(公告)号：US20160043861A1
公开(公告)日：2016-02-11
申请号：US14820266
申请日：2015-08-06
申请人： Rambus Inc.
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
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公开(公告)号：US09154291B2
公开(公告)日：2015-10-06
申请号：US14032738
申请日：2013-09-20
申请人： FUJITSU LIMITED
发明人： Hisakatsu Yamaguchi
CPC分类号： H04L7/00 , H03L7/08 , H04L7/0008 , H04L7/033 , H04L7/0338
摘要： A differential signal skew adjustment method includes: outputting a differential data signal including a first polarity signal and a second polarity signal from a transmission circuit in synchronization with a cycle of a reference clock; adjusting a phase of a detection clock obtained by dividing the reference clock in accordance with a phase of the first polarity signal; and adjusting a phase of the second polarity signal in accordance with an adjusted phase of the detection clock to adjust skew between the first polarity signal and the second polarity signal.
摘要翻译： 差分信号偏移调整方法包括：与参考时钟的周期同步地从发送电路输出包括第一极性信号和第二极性信号的差分数据信号; 调整通过根据第一极性信号的相位对参考时钟进行分频而获得的检测时钟的相位; 以及根据所述检测时钟的调整相位调整所述第二极性信号的相位，以调整所述第一极性信号和所述第二极性信号之间的偏差。
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