公开(公告)号：US10388243B2

公开(公告)日：2019-08-20

申请号：US15480358

申请日：2017-04-05

Applicant: NOVATEK Microelectronics Corp.

Inventor： Shu-Wei Chang ,  Chia-Chi Yu ,  Kuo-Jen Hsu

IPC: G09G3/36 ,  G11C19/00

Abstract: The driving system for driving a display panel includes a timing controller and a source driving circuit. The source driving circuit includes a plurality of output channels and a plurality of shift registers respectively corresponding to the output channels. The plurality of shift registers are classified into a plurality of shift register series, among which a first shift register series includes a first shift register being as one end and a second shift register being as the other end, and a second shift register series includes a third shift register being as one end and a fourth shift register being as the other end. The timing controller is connected to the first shift register, the second shift register, the third shift register, and the fourth shift register, and transmits a first start pulse to the first shift register and a second start pulse to the third shift register.

公开(公告)号：US20170213519A1

公开(公告)日：2017-07-27

申请号：US15480358

申请日：2017-04-05

Applicant: NOVATEK Microelectronics Corp.

Inventor： Shu-Wei Chang ,  Chia-Chi Yu ,  Kuo-Jen Hsu

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3648 ,  G09G2300/0413 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2340/0407 ,  G09G2370/08 ,  G11C19/00

Abstract: The driving system for driving a display panel includes a timing controller and a source driving circuit. The source driving circuit includes a plurality of output channels and a plurality of shift registers respectively corresponding to the output channels. The plurality of shift registers are classified into a plurality of shift register series, among which a first shift register series includes a first shift register being as one end and a second shift register being as the other end, and a second shift register series includes a third shift register being as one end and a fourth shift register being as the other end. The timing controller is connected to the first shift register, the second shift register, the third shift register, and the fourth shift register, and transmits a first start pulse to the first shift register and a second start pulse to the third shift register.

公开(公告)号：US20170011705A1

公开(公告)日：2017-01-12

申请号：US14842844

申请日：2015-09-02

Applicant: Novatek Microelectronics Corp.

Inventor： Ting-Chun Lin ,  Shu-Wei Chang ,  Chiu-Hung Cheng ,  Chih-Kai Yu

IPC: G09G5/00

CPC classification number: G09G3/20 ,  G09G2310/0213 ,  G09G2310/0267 ,  G09G2310/08 ,  G09G2330/022

Abstract: A gate driver and a method for adjusting output channels thereof are provided. The method includes: setting a target number of the output channels; dividing the output channels into a first channel chain and a second channel chain; enabling a scanning operation of the first channel chain according to a clock signal and counting the clock signal to obtain a counting value; and when the counting value reaching a threshold value, enabling a scanning operation of the second channel chain, wherein the threshold value is determined according to a difference value between the target number and the physical number.

Abstract translation: 提供了一种栅极驱动器及其输出通道的调整方法。 该方法包括：设置输出通道的目标数量; 将输出通道分成第一通道链和第二通道链; 根据时钟信号实现第一信道链的扫描操作，对时钟信号进行计数，得到计数值; 并且当所述计数值达到阈值时，能够进行所述第二信道链的扫描操作，其中根据所述目标号与所述物理号之间的差值来确定所述阈值。

公开(公告)号：US20150325193A1

公开(公告)日：2015-11-12

申请号：US14331235

申请日：2014-07-15

Applicant: NOVATEK Microelectronics Corp.

Inventor： Shu-Wei Chang ,  Chia-Chi Yu ,  Kuo-Jen Hsu

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0809 ,  G09G2310/027 ,  G09G2340/0407 ,  G09G2370/08

Abstract: A method for a source driving circuit utilized in a display device includes receiving an input signal by a first reception module at a first period, receiving the input signal by the first reception module and a second reception module at a second period after the first period, receiving the input signal by the second reception module and a third reception module at a third period after the second period, and outputting the input signal received by the first reception module, the second reception module and the third reception module to a display panel after the third reception module finishes reception of the input signals, wherein the second reception module is disposed between the first reception module and the third reception module.

Abstract translation: 一种在显示装置中使用的源极驱动电路的方法包括：在第一周期由第一接​​收模块接收输入信号，在第一周期之后的第二周期接收第一接收模块的输入信号和第二接收模块， 在所述第二周期之后的第三周期期间，由所述第二接收模块和第三接收模块接收所述输入信号，并且在所述第二接收模块之后的第三时段接收所述第一接收模块，所述第二接收模块和所述第三接收模块的所述输入信号 第三接收模块完成输入信号的接收，其中第二接收模块设置在第一接收模块和第三接收模块之间。

公开(公告)号：US10049606B2

公开(公告)日：2018-08-14

申请号：US14842844

申请日：2015-09-02

Applicant: Novatek Microelectronics Corp.

Inventor： Ting-Chun Lin ,  Shu-Wei Chang ,  Chiu-Hung Cheng ,  Chih-Kai Yu

IPC: G09G3/20

Abstract: A gate driver and a method for adjusting output channels thereof are provided. The method includes: setting a target number of the output channels; dividing the output channels into a first channel chain and a second channel chain; enabling a scanning operation of the first channel chain according to a clock signal and counting the clock signal to obtain a counting value; and when the counting value reaching a threshold value, enabling a scanning operation of the second channel chain, wherein the threshold value is determined according to a difference value between the target number and the physical number.