公开(公告)号：US09411668B2

公开(公告)日：2016-08-09

申请号：US14154655

申请日：2014-01-14

Applicant: NVIDIA CORPORATION

Inventor： Arijit Banerjee ,  Mahmut Ersin Sinangil ,  John W. Poulton

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/0793 ,  G11C11/419 ,  G11C29/12005 ,  G11C29/24 ,  G11C29/50

Abstract: A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance.

Abstract translation: 子系统被配置为向测试或金丝雀SRAM写入驱动器电路施加偏移电压以创建引起写入操作失败的条件。 偏移电压逐渐增加，直到在金丝雀SRAM电路中发生测试写入操作失败。 子系统然后计算实际的非测试SRAM写操作的故障概率，该操作由具有零偏移的等效驱动电路执行。 然后，子系统将结果与基准可接受概率数字进行比较。 如果计算出的故障概率大于基准可接受概率图，则启动纠正措施。 以这种方式，预期SRAM写入操作的实际故障，并且纠正措施减少其发生及其对系统性能的影响。