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    System and method for performing SRAM write assist
    1.
    发明授权
    System and method for performing SRAM write assist 有权
    用于执行SRAM写入辅助的系统和方法

    公开(公告)号：US08861290B2

    公开(公告)日：2014-10-14

    申请号：US13710314

    申请日：2012-12-10

    Applicant: NVIDIA Corporation

    Inventor： Brian Matthew Zimmer ,  Mahmut Ersin Sinangil

    IPC: G11C7/00 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C11/419

    Abstract: A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell.

    Abstract translation: 提供了一种用于执行写入辅助的方法和系统。 写入辅助电路被初始化并且开始电压崩溃以减小提供给存储单元的列电源电压。 存储单元的位线被提升到低于提供给存储单元的低电源电压的升压电压，并且由位线编码的数据被写入存储单元。

    Approach to predictive verification of write integrity in a memory driver
    2.
    发明授权
    Approach to predictive verification of write integrity in a memory driver 有权
    对存储器驱动程序中写入完整性进行预测验证的方法

    公开(公告)号：US09411668B2

    公开(公告)日：2016-08-09

    申请号：US14154655

    申请日：2014-01-14

    Applicant: NVIDIA CORPORATION

    Inventor： Arijit Banerjee ,  Mahmut Ersin Sinangil ,  John W. Poulton

    IPC: G06F11/07

    CPC classification number: G06F11/076 ,  G06F11/0793 ,  G11C11/419 ,  G11C29/12005 ,  G11C29/24 ,  G11C29/50

    Abstract: A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance.

    Abstract translation: 子系统被配置为向测试或金丝雀SRAM写入驱动器电路施加偏移电压以创建引起写入操作失败的条件。 偏移电压逐渐增加，直到在金丝雀SRAM电路中发生测试写入操作失败。 子系统然后计算实际的非测试SRAM写操作的故障概率，该操作由具有零偏移的等效驱动电路执行。 然后，子系统将结果与基准可接受概率数字进行比较。 如果计算出的故障概率大于基准可接受概率图，则启动纠正措施。 以这种方式，预期SRAM写入操作的实际故障，并且纠正措施减少其发生及其对系统性能的影响。

    High-density latch arrays
    3.
    发明授权
    High-density latch arrays 有权
    高密度锁存阵列

    公开(公告)号：US09245601B2

    公开(公告)日：2016-01-26

    申请号：US14296320

    申请日：2014-06-04

    Applicant: NVIDIA Corporation

    Inventor： Mahmut Ersin Sinangil ,  John W. Poulton ,  Brucek Kurdo Khailany ,  John H. Edmondson

    IPC: G11C8/16 ,  G11C7/10 ,  G11C8/08

    CPC classification number: G11C7/106 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104

    Abstract: A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file.

    Abstract translation: 提供了一种使用高密度锁存单元来实现存储器阵列的系统和装置。 该设备包括排列成列和行的单元阵列。 每个单元包括一个包含传输门，一对反相器和一个输出缓冲器的锁存单元。 每行锁存单元被连接到至少一个公共节点，用于寻址锁存单元行，并且每列锁存单元连接到输入信号的特定位和输出信号的特定位。 可以使用高密度锁存单元的一个或多个阵列来实现寄存器文件，以替代通常用于实现寄存器文件的SRAM单元的任何或全部。

    HIGH-DENSITY LATCH ARRAYS
    4.
    发明申请
    HIGH-DENSITY LATCH ARRAYS 有权
    高密度锁定阵列

    公开(公告)号：US20150357009A1

    公开(公告)日：2015-12-10

    申请号：US14296320

    申请日：2014-06-04

    Applicant: NVIDIA Corporation

    Inventor： Mahmut Ersin Sinangil ,  John W. Poulton ,  Brucek Kurdo Khailany ,  John H. Edmondson

    IPC: G11C7/10

    CPC classification number: G11C7/106 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104

    Abstract: A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file.

    Abstract translation: 提供了一种使用高密度锁存单元来实现存储器阵列的系统和装置。 该设备包括排列成列和行的单元阵列。 每个单元包括一个包含传输门，一对反相器和一个输出缓冲器的锁存单元。 每行锁存单元被连接到至少一个公共节点，用于寻址锁存单元行，并且每列锁存单元连接到输入信号的特定位和输出信号的特定位。 可以使用高密度锁存单元的一个或多个阵列来实现寄存器文件，以替代通常用于实现寄存器文件的SRAM单元的任何或全部。

    SYSTEM AND METHOD FOR PERFORMING ADDRESS-BASED SRAM ACCESS ASSISTS
    6.
    发明申请
    SYSTEM AND METHOD FOR PERFORMING ADDRESS-BASED SRAM ACCESS ASSISTS 有权
    用于执行基于地址的SRAM访问协助的系统和方法

    公开(公告)号：US20140204687A1

    公开(公告)日：2014-07-24

    申请号：US14147411

    申请日：2014-01-03

    Applicant: NVIDIA Corporation

    Inventor： Mahmut Ersin Sinangil ,  William J. Dally

    IPC: G11C29/52

    CPC classification number: G11C29/52 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  G11C2029/4402

    Abstract: A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.

    Abstract translation: 提供了一种用于执行基于地址的存储器访问辅助的方法和系统。 接收用于存储器访问的地址，并且基于该地址确定对与该地址相对应的至少一个存储单元启用该访问辅助。 访问辅助被应用于至少一个存储单元以执行存储器访问。

    SYSTEM AND METHOD FOR PERFORMING SRAM WRITE ASSIST
    7.
    发明申请
    SYSTEM AND METHOD FOR PERFORMING SRAM WRITE ASSIST 有权
    用于执行SRAM写协助的系统和方法

    公开(公告)号：US20140160871A1

    公开(公告)日：2014-06-12

    申请号：US13710314

    申请日：2012-12-10

    Applicant: NVIDIA CORPORATION

    Inventor： Brian Matthew Zimmer ,  Mahmut Ersin Sinangil

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C11/419

    Abstract: A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell.

    Abstract translation: 提供了一种用于执行写入辅助的方法和系统。 写入辅助电路被初始化并且开始电压崩溃以减小提供给存储单元的列电源电压。 存储单元的位线被提升到低于提供给存储单元的低电源电压的升压电压，并且由位线编码的数据被写入存储单元。

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