公开(公告)号：US20180121287A1

公开(公告)日：2018-05-03

申请号：US15340919

申请日：2016-11-01

Applicant: NVIDIA CORPORATION

Inventor： Michael Wasserman ,  Manas Mandal ,  Steven Molnar ,  Jay Gupta ,  James M. Van Dyke ,  John Welsford Brooks

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1052 ,  G06F12/0646 ,  G06F2212/1032 ,  G06F2212/403

Abstract: In accordance with embodiments of the present technology, region based selective error detection and correction techniques provide for the tradeoff between the safety of error detection and error correction (EDEC) protection, and the higher bandwidth and capacity of non-EDEC protection for different uses.