公开(公告)号：US20210294660A1

公开(公告)日：2021-09-23

申请号：US17204508

申请日：2021-03-17

Applicant: NVIDIA CORPORATION

Inventor： Yury URALSKY ,  Henry MORETON ,  Matthijs de SMEDT ,  Lei YANG

IPC: G06F9/50 ,  G06T1/20 ,  G06T1/60

Abstract: The present technology augments the GPU compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. A simple scheduling model based on scalar counters semaphores) abstract the availability of hardware resources. Resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. Semantics of the counters/sema.phores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.

公开(公告)号：US20250094232A1

公开(公告)日：2025-03-20

申请号：US18961452

申请日：2024-11-27

Applicant: NVIDIA CORPORATION

Inventor： Yury URALSKY ,  Henry MORETON ,  Matthijs de SMEDT ,  Lei YANG

IPC: G06F9/50 ,  G06T1/20 ,  G06T1/60

Abstract: The present technology augments the GPU compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. A simple scheduling model based on scalar counters (e.g., semaphores) abstract the availability of hardware resources. Resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. Semantics of the counters/semaphores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.

公开(公告)号：US20200043123A1

公开(公告)日：2020-02-06

申请号：US16053341

申请日：2018-08-02

Applicant: NVIDIA Corporation

Inventor： Rajballav DASH ,  Gregory PALMER ,  Gentaro HIROTA ,  Lacky SHAH ,  Jack CHOQUETTE ,  Emmett KILGARIFF ,  Sriharsha NIVERTY ,  Milton LEI ,  Shirish GADRE ,  Omkar PARANJAPE ,  Lei YANG ,  Rouslan DIMITROV

IPC: G06T1/20 ,  G06F9/38

Abstract: A parallel processing unit (e.g., a GPU), in some examples, includes a hardware scheduler and hardware arbiter that launch graphics and compute work for simultaneous execution on a SIMD/SIMT processing unit. Each processing unit (e.g., a streaming multiprocessor) of the parallel processing unit operates in a graphics-greedy mode or a compute-greedy mode at respective times. The hardware arbiter, in response to a result of a comparison of at least one monitored performance or utilization metric to a user-configured threshold, can selectively cause the processing unit to run one or more compute work items from a compute queue when the processing unit is operating in the graphics-greedy mode, and cause the processing unit to run one or more graphics work items from a graphics queue when the processing unit is operating in the compute-greedy mode. Associated methods and systems are also described.