公开(公告)号：US20230289211A1

公开(公告)日：2023-09-14

申请号：US17691872

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Gentaro HIROTA ,  Tanmoy MANDAL ,  Jeff TUCKEY ,  Kevin STEPHANO ,  Chen MEI ,  Shayani DEB ,  Naman GOVIL ,  Rajballav DASH ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4843 ,  G06F9/505

Abstract: A processor supports new thread group hierarchies by centralizing work distribution to provide hardware-guaranteed concurrent execution of thread groups in a thread group array through speculative launch and load balancing across processing cores. Efficiencies are realized by distributing grid rasterization among the processing cores.

公开(公告)号：US20230297426A1

公开(公告)日：2023-09-21

申请号：US17698664

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Rajballav DASH ,  Stephen JONES ,  Jack Hilaire CHOQUETTE ,  Manan PATEL ,  Ronny M. KRASHINSKY ,  Shirish GADRE ,  Lixia QIN

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5022 ,  G06F9/30098 ,  G06F9/3005 ,  G06F2209/5011

Abstract: Various embodiments include techniques for utilizing resources on a processing unit. Thread groups executing on a processor begin execution with specified resources, such as a number of registers and an amount of shared memory. During execution, one or more thread groups may determine that the thread groups have excess resources needed to execute the current functions. Such thread groups can deallocate the excess resources to a free pool. Similarly, during execution, one or more thread groups may determine that the thread groups have fewer resources needed to execute the current functions. Such thread groups can allocate the needed resources from the free pool. Further, producer thread groups that generate data for consumer thread groups can deallocate excess resources prior to completion. The consumer thread groups can allocate the excess resources and initiate execution while the producer thread groups complete execution, thereby decreasing latency between producer and consumer thread groups.

公开(公告)号：US20230289189A1

公开(公告)日：2023-09-14

申请号：US17691690

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Prakash BANGALORE PRABHAKAR ,  Gentaro HIROTA ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS ,  Rajballav DASH ,  Jeff TUCKEY ,  Jerome F. DULUK, JR. ,  Lacky SHAH ,  Luke DURANT ,  Jack CHOQUETTE ,  Eric WERNESS ,  Naman GOVIL ,  Manan PATEL ,  Shayani DEB ,  Sandeep NAVADA ,  John EDMONDSON ,  Greg PALMER ,  Wish GANDHI ,  Ravi MANYAM ,  Apoorv PARLE ,  Olivier GIROUX ,  Shirish GADRE ,  Steve HEINRICH

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

公开(公告)号：US20200043123A1

公开(公告)日：2020-02-06

申请号：US16053341

申请日：2018-08-02

Applicant: NVIDIA Corporation

Inventor： Rajballav DASH ,  Gregory PALMER ,  Gentaro HIROTA ,  Lacky SHAH ,  Jack CHOQUETTE ,  Emmett KILGARIFF ,  Sriharsha NIVERTY ,  Milton LEI ,  Shirish GADRE ,  Omkar PARANJAPE ,  Lei YANG ,  Rouslan DIMITROV

IPC: G06T1/20 ,  G06F9/38

Abstract: A parallel processing unit (e.g., a GPU), in some examples, includes a hardware scheduler and hardware arbiter that launch graphics and compute work for simultaneous execution on a SIMD/SIMT processing unit. Each processing unit (e.g., a streaming multiprocessor) of the parallel processing unit operates in a graphics-greedy mode or a compute-greedy mode at respective times. The hardware arbiter, in response to a result of a comparison of at least one monitored performance or utilization metric to a user-configured threshold, can selectively cause the processing unit to run one or more compute work items from a compute queue when the processing unit is operating in the graphics-greedy mode, and cause the processing unit to run one or more graphics work items from a graphics queue when the processing unit is operating in the compute-greedy mode. Associated methods and systems are also described.

公开(公告)号：US20230289215A1

公开(公告)日：2023-09-14

申请号：US17691621

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Greg PALMER ,  Gentaro HIROTA ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS ,  Rajballav DASH ,  Jeff TUCKEY ,  Jerome F. DULUK, JR. ,  Lacky SHAH ,  Luke DURANT ,  Jack CHOQUETTE ,  Eric WERNESS ,  Naman GOVIL ,  Manan PATEL ,  Shayani DEB ,  Sandeep NAVADA ,  John EDMONDSON ,  Prakash BANGALORE PRABHAKAR ,  Wish GANDHI ,  Ravi MANYAM ,  Apoorv PARLE ,  Olivier GIROUX ,  Shirish GADRE ,  Steve HEINRICH

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/3851 ,  G06F9/3009 ,  G06F9/544

Abstract: A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

公开(公告)号：US20230236878A1

公开(公告)日：2023-07-27

申请号：US17583957

申请日：2022-01-25

Applicant: NVIDIA CORPORATION

Inventor： Jack Hilaire CHOQUETTE ,  Rajballav DASH ,  Shayani DEB ,  Gentaro HIROTA ,  Ronny M. KRASHINSKY ,  Ze LONG ,  Chen MEI ,  Manan PATEL ,  Ming Y. SIU

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: In various embodiments, scheduling dependencies associated with tasks executed on a processor are decoupled from data dependencies associated with the tasks. Before the completion of a first task that is executing in the processor, a scheduling dependency specifying that a second task is dependent on the first task is resolved based on a pre-exit trigger. In response to the resolution of the scheduling dependency, the second task is launched on the processor.