公开(公告)号：US12197954B2

公开(公告)日：2025-01-14

申请号：US17204508

申请日：2021-03-17

Applicant: NVIDIA CORPORATION

Inventor： Yury Uralsky ,  Henry Moreton ,  Matthijs de Smedt ,  Lei Yang

IPC: G06F9/50 ,  G06T1/20 ,  G06T1/60

Abstract: The present technology augments the GPU compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. A simple scheduling model based on scalar counters (e.g., semaphores) abstract the availability of hardware resources. Resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. Semantics of the counters/semaphores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.