公开(公告)号：US09448766B2

公开(公告)日：2016-09-20

申请号：US14011631

申请日：2013-08-27

Applicant: NVIDIA CORPORATION

Inventor： Tyson Bergland ,  Michael J. M. Toksvig ,  Justin Michael Mahan

IPC: G06F7/38 ,  G06F7/57 ,  G06F9/30 ,  G06F7/544

CPC classification number: G06F7/57 ,  G06F7/5443 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/3893

Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.