公开(公告)号：US11695601B2

公开(公告)日：2023-07-04

申请号：US17402465

申请日：2021-08-13

Applicant: NVIDIA Corporation

Inventor： Sunil Rao Sudhakaran ,  Arash Zargaran-Yazd ,  Santhosh Kumar Gude ,  Seema Kumar

IPC: H04L27/02 ,  G06F1/08

CPC classification number: H04L27/02 ,  G06F1/08

Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.

公开(公告)号：US11573854B2

公开(公告)日：2023-02-07

申请号：US17523775

申请日：2021-11-10

Applicant: NVIDIA CORPORATION

Inventor： Gautam Bhatia ,  Robert Bloemer ,  Sunil Rao Sudhakaran

IPC: G06F11/10 ,  G06F3/06

Abstract: Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.

公开(公告)号：US10032710B2

公开(公告)日：2018-07-24

申请号：US14807823

申请日：2015-07-23

Applicant: NVIDIA CORPORATION

Inventor： Seunghyun Hwang ,  Vishnu Balan ,  Sunil Rao Sudhakaran

IPC: H01L23/498 ,  H01L23/52 ,  H05K1/02 ,  H05K1/11 ,  H01L23/50 ,  H01L21/48 ,  H01L23/522 ,  H01L23/00 ,  H01L23/485

Abstract: An integrated circuit (IC) system includes an IC coupled to a package. The package, in turn, is coupled to a ball grid array. The integrated circuit is electrically coupled to the ball grid array by a plurality of package through-hole (PTH) vias that penetrate through the package. Each PTH via includes a conductive element associated with a differential signaling pair. The conductive elements within a given differential signaling pair are disposed in the package at specific locations, relative to other conductive elements in other differential signaling pairs, to reduce crosstalk between those differential signaling pairs. At least one advantage of technique described herein is that the conductive elements within the package can be densely packed together without inducing excessive crosstalk. Therefore, the package can support a large number of differential signaling pairs, allowing high-throughput data communication.

公开(公告)号：US20230052588A1

公开(公告)日：2023-02-16

申请号：US17402465

申请日：2021-08-13

Applicant: NVIDIA Corporation

Inventor： Sunil Rao Sudhakaran ,  Arash Zargaran-Yazd ,  Santhosh Kumar Gude ,  Seema Kumar

IPC: H04L27/02 ,  G06F1/08

Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.