ADAPTING FORWARD ERROR CORRECTION (FEC) OR LINK PARAMETERS FOR IMPROVED POST-FEC PERFORMANCE

    公开(公告)号:US20240214134A1

    公开(公告)日:2024-06-27

    申请号:US18112406

    申请日:2023-02-21

    IPC分类号: H04L1/20 H04L1/00

    摘要: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the receiver circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

    Techniques for improving high-speed communications in a computing system

    公开(公告)号:US10728062B1

    公开(公告)日:2020-07-28

    申请号:US16287104

    申请日:2019-02-27

    IPC分类号: H04L25/03 H04L25/02

    摘要: In a computing system, various components/devices communicate with each other. For example, a microprocessor may communicate with memory or may communicate with another microprocessor over a link. Various factors such as the frequency and transmission speed of a signal can distort what is being communicated over a link. The problem becomes more pronounced as the transmission speed increases. To address this problem, devices on both ends of a link can cooperate to equalize the link. Equalization involves configuring the transmitting device to alter the signal being transmitted so that certain distortions introduced during transmission are negated by the time the signal arrives at the receiving device. Given that each link can have slightly different characteristics, appropriate equalization parameters need to be ascertained for each link. Introduced herein are improved techniques for performing equalization that are quick yet provide equalization parameters that are stable even in a noisy high-speed link.

    Receiver and transmitter adaptation using stochastic gradient hill climbing with genetic mutation

    公开(公告)号:US11381431B2

    公开(公告)日:2022-07-05

    申请号:US17326032

    申请日:2021-05-20

    IPC分类号: H04L27/01

    摘要: A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several frequency response parameters. Each frequency response parameter controls at least a portion of the frequency response of the receiver. The optimal values for the frequency response parameters are determined by modifying an initial set of values for the frequency response parameters through one or more of stochastic hill climbing operations until a performance metric associated with the receiver reaches a local maximum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the frequency response parameters.

    RECEIVER AND TRANSMITTER ADAPTATION USING STOCHASTIC GRADIENT HILL CLIMBING WITH GENETIC MUTATION

    公开(公告)号:US20210344530A1

    公开(公告)日:2021-11-04

    申请号:US17326032

    申请日:2021-05-20

    IPC分类号: H04L27/01

    摘要: A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several frequency response parameters. Each frequency response parameter controls at least a portion of the frequency response of the receiver. The optimal values for the frequency response parameters are determined by modifying an initial set of values for the frequency response parameters through one or more of stochastic hill climbing operations until a performance metric associated with the receiver reaches a local maximum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the frequency response parameters.

    INFLUENCE CLOCK DATA RECOVERY SETTLING POINT BY APPLYING DECISION FEEDBACK EQUALIZATION TO A CROSSING SAMPLE
    8.
    发明申请
    INFLUENCE CLOCK DATA RECOVERY SETTLING POINT BY APPLYING DECISION FEEDBACK EQUALIZATION TO A CROSSING SAMPLE 审中-公开
    通过将决策反馈均衡应用于交叉示例,影响时钟数据恢复确定点

    公开(公告)号:US20160226684A1

    公开(公告)日:2016-08-04

    申请号:US14988675

    申请日:2016-01-05

    IPC分类号: H04L27/01 H04L25/03 H04L7/033

    摘要: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

    摘要翻译: 一种装置,包括接收器,其被耦合以从通信链路接收输入信号,并且可操作以对通信链路的输入信号采用判决反馈均衡,并生成边缘采样信号。 该装置还包括一个定时恢复模块,其耦合到该接收器并可操作以接收该边缘采样信号并使用该边缘采样信号来产生一个数据采样相位信号,其中边沿采样信号影响数据采样相位信号的稳定点。

    ADAPTING FORWARD ERROR CORRECTION (FEC) OR LINK PARAMETERS FOR IMPROVED POST-FEC PERFORMANCE

    公开(公告)号:US20240364451A1

    公开(公告)日:2024-10-31

    申请号:US18770877

    申请日:2024-07-12

    IPC分类号: H04L1/00 H04L1/20

    CPC分类号: H04L1/0045 H04L1/203

    摘要: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from at least the receiver circuit or the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.