公开(公告)号：US20140109102A1

公开(公告)日：2014-04-17

申请号：US13651131

申请日：2012-10-12

Applicant: NVIDIA CORPORATION

Inventor： Samuel H. Duncan ,  Gary WARD ,  M. Wasiur RASHID ,  Lincoln G. GARLICK ,  Wojciech Jan Truty

IPC: G06F9/48

CPC classification number: G06F9/3887 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/5027 ,  G06F2209/5017

Abstract: A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.

Abstract translation: 多线程处理单元包括耦合到一个或多个处理引擎（例如，复制引擎，GPC等）的硬件预处理器，其通过将任务分割成更小的子任务并在处理引擎上调度子任务来实现优先技术 优先任务。 通过限制子任务的大小，可以在不切换处理引擎的上下文状态的情况下快速执行较高优先级的任务。 任务可以基于阈值大小进行细分，或者通过考虑诸如存储器系统的物理边界的其他考虑来细分。

公开(公告)号：US10095526B2

公开(公告)日：2018-10-09

申请号：US13651131

申请日：2012-10-12

Applicant: NVIDIA Corporation

Inventor： Samuel H. Duncan ,  Gary Ward ,  M. Wasiur Rashid ,  Lincoln G. Garlick ,  Wojciech Jan Truty

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50

Abstract: A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.

公开(公告)号：US09639494B2

公开(公告)日：2017-05-02

申请号：US14070147

申请日：2013-11-01

Applicant: NVIDIA CORPORATION

Inventor： Jesse Max Guss ,  Philip Browning Johnson ,  Chris Marriott ,  Wojciech Jan Truty

IPC: G06F13/20 ,  G06F11/22 ,  G06F13/40 ,  H01H85/04

CPC classification number: G06F13/4072 ,  G06F11/22 ,  H01H85/04

Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.