公开(公告)号：US20150042664A1

公开(公告)日：2015-02-12

申请号：US14026410

申请日：2013-09-13

Applicant: NVIDIA Corporation

Inventor： Andrew CURRID ,  Franck DIARD ,  Chenghuan JIA ,  Parag KULKARNI

IPC: G06T1/20 ,  G09G5/00 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F3/1438 ,  G06F9/455 ,  G06F9/46 ,  G06F9/5077 ,  G09G3/003 ,  G09G5/363 ,  G09G2360/06 ,  G09G2370/022

Abstract: A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.

Abstract translation: 用于处理图形数据的设备包括多个图形处理单元。 每个图形处理单元可以对应于虚拟化的操作系统。 每个图形处理单元可以包括指示3D类代码的配置寄存器和指示I / O周期解码被禁用的命令寄存器。 该设备可以被配置为将配置寄存器值发送到指示VGA兼容类代码的虚拟操作系统。 该设备可以被配置为向指示执行I / O周期解码的虚拟化操作系统发送命令寄存器值。 以这种方式，设备的传统总线架构可能不限制部署在设备中的图形处理单元的数量。