公开(公告)号：US11983566B2

公开(公告)日：2024-05-14

申请号：US17374361

申请日：2021-07-13

Applicant: NVIDIA Corporation

Inventor： Yilin Zhang ,  Geng Chen ,  Yan Zhou ,  Qifei Fan ,  Prashant Gaikwad

IPC: G06F9/50 ,  G06F9/48 ,  G06N3/063

CPC classification number: G06F9/5027 ,  G06F9/4881 ,  G06N3/063

Abstract: Apparatuses, systems, and techniques for scheduling deep learning tasks in hardware are described. One accelerator circuit includes multiple fixed-function circuits that each processes a different layer type of a neural network. A scheduler circuit receives state information associated with a respective layer being processed by a respective fixed-function circuit and dependency information that indicates a layer dependency condition for the respective layer. The scheduler circuit determines that the layer dependency condition is satisfied using the state information and the dependency information and enables the fixed-function circuit to process the current layer at the respective fixed-function circuit.

公开(公告)号：US20220382592A1

公开(公告)日：2022-12-01

申请号：US17374361

申请日：2021-07-13

Applicant: NVIDIA Corporation

Inventor： Yilin Zhang ,  Geng Chen ,  Yan Zhou ,  Qifei Fan ,  Prashant Gaikwad

IPC: G06F9/50 ,  G06F9/48 ,  G06N3/063

Abstract: Apparatuses, systems, and techniques for scheduling deep learning tasks in hardware are described. One accelerator circuit includes multiple fixed-function circuits that each processes a different layer type of a neural network. A scheduler circuit receives state information associated with a respective layer being processed by a respective fixed-function circuit and dependency information that indicates a layer dependency condition for the respective layer. The scheduler circuit determines that the layer dependency condition is satisfied using the state information and the dependency information and enables the fixed-function circuit to process the current layer at the respective fixed-function circuit.