USER-INTERACTIVE ENVIRONMENTS FOR AUTOMATING MICROSERVICE CONFIGURATION, PACKAGING, AND DEPLOYMENT

    公开(公告)号:US20250063097A1

    公开(公告)日:2025-02-20

    申请号:US18450267

    申请日:2023-08-15

    Abstract: Approaches presented herein provide systems and methods for generating a standardized specification and associated interface for application development. One or more microservices may be selected and graphically represented within an interface that receives connection information from one or more users. Connected microservices may have one or more configuration specifications that are auto-populated based, at least, on operation parameters for an associated application and/or related microservices. A development environment may provide for visual representations of connections between microservices along with configuration parameters and validation services. Deployment information may then be generated based on the configuration in the representations.

    HARDWARE CIRCUIT FOR DEEP LEARNING TASK SCHEDULING

    公开(公告)号:US20220382592A1

    公开(公告)日:2022-12-01

    申请号:US17374361

    申请日:2021-07-13

    Abstract: Apparatuses, systems, and techniques for scheduling deep learning tasks in hardware are described. One accelerator circuit includes multiple fixed-function circuits that each processes a different layer type of a neural network. A scheduler circuit receives state information associated with a respective layer being processed by a respective fixed-function circuit and dependency information that indicates a layer dependency condition for the respective layer. The scheduler circuit determines that the layer dependency condition is satisfied using the state information and the dependency information and enables the fixed-function circuit to process the current layer at the respective fixed-function circuit.

    Hardware circuit for deep learning task scheduling

    公开(公告)号:US11983566B2

    公开(公告)日:2024-05-14

    申请号:US17374361

    申请日:2021-07-13

    CPC classification number: G06F9/5027 G06F9/4881 G06N3/063

    Abstract: Apparatuses, systems, and techniques for scheduling deep learning tasks in hardware are described. One accelerator circuit includes multiple fixed-function circuits that each processes a different layer type of a neural network. A scheduler circuit receives state information associated with a respective layer being processed by a respective fixed-function circuit and dependency information that indicates a layer dependency condition for the respective layer. The scheduler circuit determines that the layer dependency condition is satisfied using the state information and the dependency information and enables the fixed-function circuit to process the current layer at the respective fixed-function circuit.

    CONFIGURING MACHINE LEARNING MODELS FOR TRAINING AND DEPLOYMENT USING GRAPHICAL COMPONENTS

    公开(公告)号:US20220391176A1

    公开(公告)日:2022-12-08

    申请号:US17806056

    申请日:2022-06-08

    Abstract: Embodiments of the present disclosure relate to applications and platforms for configuring machine learning models for training and deployment using graphical components in a development environment. For example, systems and methods are disclosed that relate to determining one or more machine learning models and one or more processing operations corresponding to the one or more machine learning models. Further, a model component may be generated using the one or more machine learning models, the one or more processing operations, and one or more extension libraries in which the one or more extension libraries indicate one or more deployment parameters related to the one or more machine learning models. The model component may accordingly provide data that may be used to be able to use and deploy the one or more machine learning models.

    MACHINE LEARNING APPLICATION DEPLOYMENT USING USER-DEFINED PIPELINE

    公开(公告)号:US20220391175A1

    公开(公告)日:2022-12-08

    申请号:US17806055

    申请日:2022-06-08

    Abstract: Systems and methods are disclosed that relate to graphically representing different components (e.g., software modules, libraries, interfaces, or other blocks of code) that may be included in an application, linking the components in an ordered sequence to embody the application, and deploying the application to perform a task. The components may be displayed and represented as graphical components in a graphical application editor, or any other development environment. The graphical application editor may perform various operations with respect to the graphical components and the components respectively represented by and corresponding therewith. The operations may include facilitation of linking implemented instances of the graphical component objects together and/or developing the application by linking the underlying code associated with the graphical component objects according to the linking of the graphical component objects.

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