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    SYSTEM AND METHOD FOR REDUCED CACHE MODE
    3.
    发明申请
    SYSTEM AND METHOD FOR REDUCED CACHE MODE 审中-公开
    用于减少高速缓存模式的系统和方法

    公开(公告)号：US20140136793A1

    公开(公告)日：2014-05-15

    申请号：US13676041

    申请日：2012-11-13

    申请人： NVIDIA CORPORATION

    发明人： James Patrick Robertson ,  Oren Rubinstein ,  Michael A. Woodmansee ,  Don Bittel ,  Stephen D. Lew ,  Edward Riegelsberger ,  Brad W. Simeral ,  Gregory Alan Muthler ,  John Matthew Burgess

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0891 ,  G06F2212/601 ,  Y02D10/13

    摘要： A system and method are described for dynamically changing the size of a computer memory such as level 2 cache as used in a graphics processing unit. In an embodiment, a relatively large cache memory can be implemented in a computing system so as to meet the needs of memory intensive applications. But where cache utilization is reduced, the capacity of the cache can be reduced. In this way, power consumption is reduced by powering down a portion of the cache.

    摘要翻译： 描述了用于动态地改变诸如图形处理单元中使用的诸如2级缓存的计算机存储器的大小的系统和方法。 在一个实施例中，可以在计算系统中实现相对较大的高速缓冲存储器，以便满足存储器密集型应用的需要。 但是，在缓存利用率降低的地方，缓存的容量可以降低。 以这种方式，通过关闭高速缓存的一部分来降低功耗。

    Dynamically detecting uniformity and eliminating redundant computations to reduce power consumption
    4.
    发明授权
    Dynamically detecting uniformity and eliminating redundant computations to reduce power consumption 有权

    公开(公告)号：US11055097B2

    公开(公告)日：2021-07-06

    申请号：US14048647

    申请日：2013-10-08

    申请人： NVIDIA CORPORATION

    发明人： Gary M. Tarolli ,  John H. Edmondson ,  John Matthew Burgess ,  Robert Ohannessian

    IPC分类号： G06F9/30 ,  G06F9/38

    摘要： One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of threads, the SM designates one thread as the anchor thread. The SM disables execution units assigned to all of the threads except the anchor thread. The anchor execution unit, assigned to the anchor thread, executes the operation on the uniform set of input operands. Subsequently, the SM sets the outputs of the non-anchor threads included in the uniform group of threads to equal the value of the anchor execution unit output.