公开(公告)号：US20230289304A1

公开(公告)日：2023-09-14

申请号：US17691276

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Alexander L. Minkin ,  Alan Kaatz ,  Oliver Giroux ,  Jack Choquette ,  Shirish Gadre ,  Manan Patel ,  John Tran ,  Ronny Krashinsky ,  Jeff Schottmiller

IPC: G06F13/16

CPC classification number: G06F13/1663

Abstract: A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and/or an external memory.

公开(公告)号：US12141082B2

公开(公告)日：2024-11-12

申请号：US17691276

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Alexander L. Minkin ,  Alan Kaatz ,  Oliver Giroux ,  Jack Choquette ,  Shirish Gadre ,  Manan Patel ,  John Tran ,  Ronny Krashinsky ,  Jeff Schottmiller

IPC: G06F13/16

Abstract: A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and/or an external memory.