公开(公告)号：US20230289242A1

公开(公告)日：2023-09-14

申请号：US17691296

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Timothy GUO ,  Jack CHOQUETTE ,  Shirish GADRE ,  Olivier GIROUX ,  Carter EDWARDS ,  John EDMONDSON ,  Manan PATEL ,  Raghavan MADHAVAN, JR. ,  Jessie HUANG ,  Peter NELSON ,  Ronny KRASHINSKY

IPC: G06F9/52

CPC classification number: G06F9/522 ,  G06F2209/521

Abstract: A new transaction barrier synchronization primitive enables executing threads and asynchronous transactions to synchronize across parallel processors. The asynchronous transactions may include transactions resulting from, for example, hardware data movement units such as direct memory units, etc. A hardware synchronization circuit may provide for the synchronization primitive to be stored in a cache memory so that barrier operations may be accelerated by the circuit. A new wait mechanism reduces software overhead associated with waiting on a barrier.