公开(公告)号：US08813019B1

公开(公告)日：2014-08-19

申请号：US13873263

申请日：2013-04-30

Applicant: NVIDIA Corporation

Inventor： Avinash Rath ,  Sanjith Sleeba ,  Ashish Kumar

IPC: G06F17/50 ,  G01R31/28 ,  G01R27/28 ,  G06F11/07

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F2217/14

Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.

Abstract translation: 一种方法包括通过通信地耦合到存储器的计算设备的处理器读取作为其验证的一部分的电子电路的设计。 该方法还包括通过处理器提取参与验证的测试算法的一组优化的指令，使得该组优化的指令覆盖与电子电路的设计相关联的逻辑功能的最大部分。 此外，该方法包括通过处理器执行与优化的指令集相关的测试算法，以减少电子电路的设计的验证时间。