-
公开(公告)号：US10886959B2
公开(公告)日：2021-01-05
申请号：US16366291
申请日：2019-03-27
Applicant: NXP B.V.
Inventor： Andreas Johannes Köllmann , Bernard Burdiek
IPC: H04B1/16 , H03K17/687 , H03F1/56 , H03F3/45
Abstract: Embodiments are directed to a buffer circuit that includes a first circuit and a second circuit. The first and second circuits include sets of transistors along pairs of related signal paths, each of the transistors being driven in response to two related input signals having different but related phases. The first circuit generates a first related output signal in response to one of the pairs of related signal paths and the second circuit generates a second output signal in response to another of the pairs of related signal paths. The first and second circuits provide a linear transfer function across one of the first and one of the second sets of transistors via one of the first pair and second pair of related signal paths.
-
公开(公告)号：US09479141B2
公开(公告)日：2016-10-25
申请号：US14941941
申请日：2015-11-16
Applicant: NXP B.V.
Inventor： Andreas Johannes Köllmann , Steffen Rode , Joachim Utzig , Joerg Syré
CPC classification number: H03H11/1213 , G05F1/56 , H03H7/06 , H03H11/1217 , H03H11/245
Abstract: A low-pass filter comprising: a filter input terminal; a filter output terminal; a filter FET configured to provide a resistance between the filter input terminal and the filter output terminal; a filter capacitor connected between the filter output terminal and a reference terminal; a bias FET configured to provide a bias voltage to the filter FET; a buffer connected between the filter input terminal and the bias FET, the buffer configured to source a bias current for the bias FET; and an offset voltage source configured to contribute to the bias voltage provided to the filter FET.
Abstract translation: 一种低通滤波器，包括：滤波器输入端; 滤波器输出端子; 滤波器FET，被配置为提供所述滤波器输入端子和所述滤波器输出端子之间的电阻; 滤波电容器连接在滤波器输出端子和参考端子之间; 偏置FET，被配置为向所述滤波器FET提供偏置电压; 连接在所述滤波器输入端子和所述偏置FET之间的缓冲器，所述缓冲器被配置为为所述偏置FET馈送偏置电流; 以及被配置为有助于提供给所述滤波器FET的偏置电压的偏移电压源。
-
公开(公告)号：US12216226B2
公开(公告)日：2025-02-04
申请号：US17661944
申请日：2022-05-04
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Cristian Pavao Moreira , Andreas Johannes Köllmann
Abstract: Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).
-
Patent Agency Ranking
公开(公告)号：US20240085476A1
公开(公告)日：2024-03-14
申请号：US17943288
申请日：2022-09-13
Applicant: NXP B.V.
Inventor： Andreas Johannes Köllmann , Ulrich Moehlmann
IPC: G01R31/317 , G01R31/3177 , G01R31/319
CPC classification number: G01R31/31727 , G01R31/3177 , G01R31/31922 , H03K5/1565
Abstract: A system includes a phase-shift to duty-cycle converter and a low pass filter. The phase-shift to duty-cycle converter has a first input for a reference clock and a second input for a phase-shifted clock that is phase-shifted relative to the reference clock. The low pass filter has an input coupled to an output of the phase-shift to duty-cycle converter and an output for an output signal. In some implementations, the phase-shift to duty-cycle converter includes a simple logic gate and a reset-set flip flop. The simple logic gate has a third input coupled to the first input and a fourth input coupled to the second input, and the reset-set flip flop has a fifth input coupled to the first input and a sixth input coupled to the second input. The low pass filter is coupled to the output of one of the simple logic gate and the reset-set flip flop.
-
公开(公告)号：US20220365173A1
公开(公告)日：2022-11-17
申请号：US17661944
申请日：2022-05-04
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Cristian Pavao Moreira , Andreas Johannes Köllmann
Abstract: Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).
-
公开(公告)号：US10826505B1
公开(公告)日：2020-11-03
申请号：US16449711
申请日：2019-06-24
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Andreas Johannes Köllmann , Christian Scherner
Abstract: A hardware device includes a frequency lock loop (FLL) that includes a phase loop filter, and a phase lock loop (PLL) such as an all digital PLL (ADPLL) that includes a frequency loop filter. A controller provides a first control signal to the FLL and a second control signal to the PLL when the device operates the same. The device can also include a digital controlled oscillator (DCO) and part of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a divider receive an input from the DCO. The controller forms a first loop with the first filter, the TDC, and the divider, and the controller forms a second loop with the second filter, the TDC, and the divider.
-
公开(公告)号：US20200313709A1
公开(公告)日：2020-10-01
申请号：US16366291
申请日：2019-03-27
Applicant: NXP B.V.
Inventor： Andreas Johannes Köllmann , Bernard Burdiek
IPC: H04B1/16 , H03K17/687 , H03F1/56 , H03F3/45
Abstract: Embodiments are directed to a buffer circuit that includes a first circuit and a second circuit. The first and second circuits include sets of transistors along pairs of related signal paths, each of the transistors being driven in response to two related input signals having different but related phases. The first circuit generates a first related output signal in response to one of the pairs of related signal paths and the second circuit generates a second output signal in response to another of the pairs of related signal paths. The first and second circuits provide a linear transfer function across one of the first and one of the second sets of transistors via one of the first pair and second pair of related signal paths.
-
公开(公告)号：US20160149559A1
公开(公告)日：2016-05-26
申请号：US14941941
申请日：2015-11-16
Applicant: NXP B.V.
Inventor： Andreas Johannes Köllmann , Steffen Rode , Joachim Utzig , Joerg Syré
IPC: H03H11/12
CPC classification number: H03H11/1213 , G05F1/56 , H03H7/06 , H03H11/1217 , H03H11/245
Abstract: A low-pass filter comprising: a filter input terminal; a filter output terminal; a filter FET configured to provide a resistance between the filter input terminal and the filter output terminal; a filter capacitor connected between the filter output terminal and a reference terminal; a bias FET configured to provide a bias voltage to the filter FET; a buffer connected between the filter input terminal and the bias FET, the buffer configured to source a bias current for the bias FET; and an offset voltage source configured to contribute to the bias voltage provided to the filter FET.
Abstract translation: 一种低通滤波器，包括：滤波器输入端; 滤波器输出端子; 滤波器FET，被配置为提供所述滤波器输入端子和所述滤波器输出端子之间的电阻; 滤波电容器连接在滤波器输出端子和参考端子之间; 偏置FET，被配置为向所述滤波器FET提供偏置电压; 连接在所述滤波器输入端子和所述偏置FET之间的缓冲器，所述缓冲器被配置为为所述偏置FET馈送偏置电流; 以及被配置为有助于提供给所述滤波器FET的偏置电压的偏移电压源。
-
-
-
-
-
-
-
Search Results
8
records
(took 0.016 seconds)
