公开(公告)号：US20250093899A1

公开(公告)日：2025-03-20

申请号：US18468263

申请日：2023-09-15

Applicant: NXP B.V.

Inventor： Joachim Josef Maria Kruecken ,  Andreas Laudenbach

IPC: G05F3/08 ,  H03K3/037 ,  H03K5/24

Abstract: A receiver circuit receives an input voltage waveform from a single wire and generates an output bit stream. The receiver includes a voltage determination circuit which indicates whether a voltage level of the input voltage waveform has one of a high level that is higher than a high voltage threshold, a low level that is lower than a low voltage threshold, or a mid level that is between the high and low voltage levels. The receiver includes a bit value generator which provides a next bit value of the output bit stream as a first value when the voltage level is the high level, as a second value when the voltage level is the low level, and as a same value as an immediately previous bit value of the output bit stream when the voltage level is the mid level. The first and second values correspond to opposite logic states.