公开(公告)号：US20240421920A1

公开(公告)日：2024-12-19

申请号：US18741251

申请日：2024-06-12

Applicant: NXP B.V.

Inventor： Zahran Hajji ,  Ayoub Rifai ,  Thierry Mesnard ,  Florent Jérémy Alexis Cilici

IPC: H04B17/19 ,  H04B17/10

Abstract: A method includes techniques for identifying the phase step of one transmitter while conducting phase difference measurements between two transmitters in a multi-transmitter radar device. The method includes setting a first phase of a first transmitter in the multi-transmitter device to a fixed phase value and setting a second phase of a second transmitter in the multi-transmitter device to an initial phase value, varying the second phase of the second transmitter from the initial phase value to a final phase value and performing a sample measurement at each variation to obtain a plurality of intermediate frequency (IF) samples; and transforming the plurality of IF samples into complex samples. The method then includes determining one or more phase steps of the second transmitter based on the complex samples.

公开(公告)号：US20240134647A1

公开(公告)日：2024-04-25

申请号：US18483064

申请日：2023-10-09

Applicant: NXP B.V.

Inventor： Paul Wielage ,  Ayoub Rifai ,  Dominique Delbecq

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30098

Abstract: A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.