公开(公告)号：US20180046211A1

公开(公告)日：2018-02-15

申请号：US15232373

申请日：2016-08-09

Applicant: NXP B.V.

Inventor： Andre Luis Vilas Boas ,  Dale McQuirk ,  Miten Nagda ,  Richard Titov Lara Saez

IPC: G05F1/575 ,  G11C5/14

CPC classification number: G05F1/575 ,  G11C5/147

Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.

公开(公告)号：US10444778B2

公开(公告)日：2019-10-15

申请号：US15232373

申请日：2016-08-09

Applicant: NXP B.V.

Inventor： Andre Luis Vilas Boas ,  Dale McQuirk ,  Miten Nagda ,  Richard Titov Lara Saez

IPC: G05F1/10 ,  G05F1/575 ,  G11C5/14

Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.