-
公开(公告)号：US11644487B2
公开(公告)日：2023-05-09
申请号：US17236227
申请日：2021-04-21
Applicant: NXP B.V.
Inventor： Andre Luis Vilas Boas , Bruno Caceres Carrilho , Andre Gunther , Jeffrey Alan Goswick
IPC: G01R19/165 , G08B21/18 , H03K17/687 , H03K5/24
CPC classification number: G01R19/16576 , G08B21/182 , H03K5/24 , H03K17/687
Abstract: An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.
-
公开(公告)号：US20220341975A1
公开(公告)日：2022-10-27
申请号：US17236227
申请日：2021-04-21
Applicant: NXP B.V.
Inventor： Andre Luis Vilas Boas , Bruno Caceres Carrilho , Andre Gunther , Jeffrey Alan Goswick
IPC: G01R19/165 , H03K5/24 , H03K17/687 , G08B21/18
Abstract: An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.
-
公开(公告)号：US20180046211A1
公开(公告)日：2018-02-15
申请号：US15232373
申请日：2016-08-09
Applicant: NXP B.V.
Inventor： Andre Luis Vilas Boas , Dale McQuirk , Miten Nagda , Richard Titov Lara Saez
Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.
-
公开(公告)号：US10444778B2
公开(公告)日：2019-10-15
申请号：US15232373
申请日：2016-08-09
Applicant: NXP B.V.
Inventor： Andre Luis Vilas Boas , Dale McQuirk , Miten Nagda , Richard Titov Lara Saez
Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.
-
-
-
Search Results
4
records
(took 0.009 seconds)
