公开(公告)号：US20240353888A1

公开(公告)日：2024-10-24

申请号：US18640347

申请日：2024-04-19

Applicant: NXP B.V.

Inventor： Andreas Lentz ,  David Paul Price

IPC: G06F1/10 ,  G06F1/08

CPC classification number: G06F1/10 ,  G06F1/08

Abstract: The present disclosure relates to a clock signal monitoring unit comprising first, second and third flip-flops, first and second XOR gates and a delay element being functionally interconnected in a specific way. The proposed clock signal monitoring unit can detect both a rising edge glitch and a falling edge glitch. In this way there is provided an area saving device, which does not require any trimming efforts, which can save a lot of space and time. Furthermore, the clock signal monitoring unit can have low electric power consumption because it uses as few as four clocked flip-flops implemented via Register Transfer Logic having an already tuned delay element. This makes it useful for designs that use both edges of the clock for correct operation.