公开(公告)号：US11645155B2

公开(公告)日：2023-05-09

申请号：US17249155

申请日：2021-02-22

申请人： NXP B.V.

发明人： Arjun Pal Chowdhury ,  Nancy Hing-Che Amedeo ,  Jehoda Refaeli

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G06F13/40

CPC分类号： G06F11/141 ,  G06F11/0772 ,  G06F11/1428 ,  G06F11/1441 ,  G06F13/4027 ,  G06F13/4068

摘要： A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

公开(公告)号：US20220269563A1

公开(公告)日：2022-08-25

申请号：US17249155

申请日：2021-02-22

申请人： NXP B.V.

发明人： Arjun Pal Chowdhury ,  Nancy Hing-Che Amedeo ,  Jehoda Refaeli

IPC分类号： G06F11/14 ,  G06F11/07 ,  G06F13/40

摘要： A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

公开(公告)号：US12072757B2

公开(公告)日：2024-08-27

申请号：US17976623

申请日：2022-10-28

申请人： NXP B.V.

发明人： Ankush Sethi ,  Rohit Kumar Kaul ,  James Andrew Welker ,  Vaibhav Kumar ,  Jehoda Refaeli

IPC分类号： G06F11/07

CPC分类号： G06F11/079 ,  G06F11/0721

摘要： An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.