公开(公告)号：US09202588B1

公开(公告)日：2015-12-01

申请号：US14494263

申请日：2014-09-23

Applicant: NXP B.V.

Inventor： Rajat Kohli ,  Patrick Van de steeg ,  Jwalant Mishra ,  Pankaj Agarwal

IPC: G11C17/00 ,  G11C17/12

CPC classification number: G11C17/12 ,  G11C11/5692 ,  G11C17/126

Abstract: Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.

Abstract translation: 公开了一种ROM存储器件，其包括存储单元的多个行和列，每个存储单元包括位线对和晶体管，用于在其中存储两位数据，以及设置在相邻的位线对对之间的虚拟接地线， 其中位线对和虚拟接地线用于读取存储在存储单元中的数据。