公开(公告)号：US09202588B1

公开(公告)日：2015-12-01

申请号：US14494263

申请日：2014-09-23

Applicant: NXP B.V.

Inventor： Rajat Kohli ,  Patrick Van de steeg ,  Jwalant Mishra ,  Pankaj Agarwal

IPC: G11C17/00 ,  G11C17/12

CPC classification number: G11C17/12 ,  G11C11/5692 ,  G11C17/126

Abstract: Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.

Abstract translation: 公开了一种ROM存储器件，其包括存储单元的多个行和列，每个存储单元包括位线对和晶体管，用于在其中存储两位数据，以及设置在相邻的位线对对之间的虚拟接地线， 其中位线对和虚拟接地线用于读取存储在存储单元中的数据。

公开(公告)号：US20240203480A1

公开(公告)日：2024-06-20

申请号：US18535443

申请日：2023-12-11

Applicant: NXP B.V.

Inventor： Prokash Ghosh ,  Jyotirmoy Ghosh ,  Glenn Charles Abeln ,  Dwarka Prasad ,  Rajat Kohli ,  Jainendra Singh ,  Jwalant Kumar Mishra

IPC: G11C11/4078 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4078 ,  G11C11/4074 ,  G11C11/4076

Abstract: A memory power control unit, MPCU, is provided for preventing unauthorised access to data stored in a volatile memory, the MPCU comprising a power controller comprising an input configured to receive a signal from a tamper detection circuit, a first supply input configured 5 to receive a first supply voltage, a first reference input configured to receive a first reference voltage, a supply output configured to output a supply voltage to the volatile memory, a reference output configured to output a reference voltage to the volatile memory, wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output a reduced supply voltage via the supply 10 output for a first predetermined time period, wherein the reduced supply voltage is less than the first supply voltage.

公开(公告)号：US10236071B1

公开(公告)日：2019-03-19

申请号：US15700152

申请日：2017-09-10

Applicant: NXP B.V.

Inventor： Rajat Kohli ,  Patrick Van De Steeg ,  Jwalant Kumar Mishra ,  Pankaj Agarwal

IPC: G11C17/12 ,  G11C11/40 ,  G11C11/56

Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

公开(公告)号：US20190080777A1

公开(公告)日：2019-03-14

申请号：US15700152

申请日：2017-09-10

Applicant: NXP B.V.

Inventor： Rajat Kohli ,  Patrick Van de Steeg ,  Jwalant Kumar Mishra ,  Pankaj Agarwal

IPC: G11C17/12 ,  G11C11/56 ,  G11C11/40

Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

公开(公告)号：US09691496B1

公开(公告)日：2017-06-27

申请号：US15018194

申请日：2016-02-08

Applicant: NXP B.V.

Inventor： Rajat Kohli ,  Patrick van de Steeg ,  Jwalant Kumar Mishra ,  Pankaj Agarwal

IPC: G11C17/00 ,  G11C17/12

CPC classification number: G11C17/126 ,  G11C11/5692 ,  G11C17/12

Abstract: Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells.