公开(公告)号：US20220285564A1

公开(公告)日：2022-09-08

申请号：US17192060

申请日：2021-03-04

Applicant: NXP B.V.

Inventor： Saumitra Raj Mehrotra ,  Kejun Xia

IPC: H01L29/866 ,  H01L29/66 ,  H01L21/265

Abstract: A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.

公开(公告)号：US11640997B2

公开(公告)日：2023-05-02

申请号：US17192060

申请日：2021-03-04

Applicant: NXP B.V.

Inventor： Saumitra Raj Mehrotra ,  Kejun Xia

IPC: H01L29/866 ,  H01L21/265 ,  H01L29/66

Abstract: A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.