公开(公告)号：US11520708B2

公开(公告)日：2022-12-06

申请号：US16707515

申请日：2019-12-09

Applicant: NXP B.V.

Inventor： Marcel Rene van Loon ,  Bruce Murray

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/02 ,  G06F12/1018 ,  H04L9/06

Abstract: A memory system, comprising: i) a first electronic device comprising a processor, ii) a second electronic device being external to the first electronic device and comprising a memory, wherein the memory stores a memory image over at least a part of a data set stored on the memory, and iii) a hash value related to the memory image. The first electronic device and the second electronic device are coupled such that the processor has at least partial control over the second electronic device. The processor is configured to, when updating the data set stored on the memory of the second electronic device, also update the hash value related to the memory image using an incremental hashing operation so that only those parts of the memory image are processed that have changed.