公开(公告)号：US11995442B2

公开(公告)日：2024-05-28

申请号：US17658356

申请日：2022-04-07

Applicant: NXP B.V.

Inventor： Paul Wielage ,  Mathias Martinus van Ansem ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30152

Abstract: A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.

公开(公告)号：US20220342669A1

公开(公告)日：2022-10-27

申请号：US17658356

申请日：2022-04-07

Applicant: NXP B.V.

Inventor： Paul Wielage ,  Mathias Martinus van Ansem ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

IPC: G06F9/30 ,  G06F9/445 ,  G06F9/54

Abstract: A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.