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    Recycling capacitance energy from active mode to low power mode
    2.
    发明授权
    Recycling capacitance energy from active mode to low power mode 有权

    公开(公告)号：US11163346B2

    公开(公告)日：2021-11-02

    申请号：US16118749

    申请日：2018-08-31

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor ,  Kristof Blutman ,  Juan Diego Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Jurgen Geerlings ,  Hamed Fatemi

    IPC: G06F1/26 ,  G06F1/32 ,  H02M3/07 ,  H02M3/137

    Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.

    HUMAN-MACHINE-INTERFACE SYSTEM
    3.
    发明申请
    HUMAN-MACHINE-INTERFACE SYSTEM 审中-公开

    公开(公告)号：US20180300138A1

    公开(公告)日：2018-10-18

    申请号：US15943926

    申请日：2018-04-03

    Applicant: NXP B.V.

    Inventor： Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Gonzalo Moro Pérez ,  Hendrik Corporaal

    IPC: G06F9/30 ,  G06N3/063 ,  G06F17/15 ,  G06K9/00 ,  G06K9/62

    Abstract: A human-machine-interface system comprising: register-file-memory, configured to store input-data; a first-processing-element-slice, a second-processing-element-slice, and a controller. Each of the processing-slices comprise: a register configured to store register-data; and a processing-element configured to apply an arithmetic and logic operation on the register-data in order to provide convolution-output-data. The controller is configured to: load input-data from the register-file-memory into the first-register as the first-register-data; and load: (i) input-data from the register-file-memory, or (ii) the first-register-data from the first-register, into the second-register as the second-register-data.

    RECYCLING CAPACITANCE ENERGY FROM ACTIVE MODE TO LOW POWER MODE
    5.
    发明申请
    RECYCLING CAPACITANCE ENERGY FROM ACTIVE MODE TO LOW POWER MODE 审中-公开

    公开(公告)号：US20200073453A1

    公开(公告)日：2020-03-05

    申请号：US16118749

    申请日：2018-08-31

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor ,  Kristof Blutman ,  Juan Diego Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Jurgen Geerlings ,  Hamed Fatemi

    IPC: G06F1/26 ,  H02M3/137 ,  H02M3/07

    Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.

    INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND INSTRUCTION SCHEDULING METHOD
    6.
    发明申请
    INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND INSTRUCTION SCHEDULING METHOD 有权
    集成电路，电子设备和指令调度方法

    公开(公告)号：US20140258686A1

    公开(公告)日：2014-09-11

    申请号：US14195657

    申请日：2014-03-03

    Applicant: NXP B.V.

    Inventor： Hamed Fatemi ,  Jose Pineda de Gyvez ,  Juan Echeverri Escobar

    IPC: G06F9/30

    CPC classification number: G06F9/30145 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

    Abstract: An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality of instructions and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies. The integrated circuit is operable in a first power mode and a second power mode. The second power mode is a reduced power mode compared to the first power mode and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies.

    Abstract translation: 一种集成电路，包括一组数据处理单元，包括第一数据处理单元和至少一个以可变频率工作的第二数据处理单元。 集成电路还包括指令调度器，其适于评估接收的多个指令中的各个指令之间的数据依赖性，并且将指令分配给第一数据处理单元和至少一个第二数据处理单元，用于根据所述数据依赖性进行并行执行 。 集成电路可在第一功率模式和第二功率模式下操作。 第二功率模式是与第一功率模式相比的降低功率模式，并且适于根据评估数据调整第二数据处理单元和第二功率模式中的至少一个第二数据处理单元的工作频率 依赖关系。

    PROCESSOR AND INSTRUCTION SET
    8.
    发明申请
    PROCESSOR AND INSTRUCTION SET 有权

    公开(公告)号：US20220342669A1

    公开(公告)日：2022-10-27

    申请号：US17658356

    申请日：2022-04-07

    Applicant: NXP B.V.

    Inventor： Paul Wielage ,  Mathias Martinus van Ansem ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

    IPC: G06F9/30 ,  G06F9/445 ,  G06F9/54

    Abstract: A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.

    APPARATUS FOR PROCESSING A SIGNAL
    9.
    发明申请
    APPARATUS FOR PROCESSING A SIGNAL 审中-公开

    公开(公告)号：US20200090040A1

    公开(公告)日：2020-03-19

    申请号：US16566991

    申请日：2019-09-11

    Applicant: NXP B.V. ,  TECHNISCHE UNIVERSITEIT EINDHOVEN

    Inventor： Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Emad Ayman Taleb Ibrahim

    IPC: G06N3/08 ,  G06N20/10 ,  G10L15/16 ,  G06F3/01

    Abstract: An apparatus for processing a signal for input to a neural network, the apparatus configured to: receive a signal comprising a plurality of samples of an analog signal over time; determine at least one frame comprising a group of consecutive samples of the signal, wherein the or each frame includes a first number of samples; for each frame, determine a set of correlation values comprising a second number of correlation values, the second number less than the first number, each correlation value of the set of correlation values based on an autocorrelation of the frame at a plurality of different time lags; provide an output based on the set of correlation values corresponding to the or each of the frames for a neural network for one or more of classification of the analog signal by the neural network and training the neural network based on a predetermined classification.

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