公开(公告)号：US11435940B2

公开(公告)日：2022-09-06

申请号：US17248661

申请日：2021-02-02

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Mohamed Azimane

IPC: G06F3/06 ,  G11C29/04 ,  G11C29/36 ,  G11C29/18

Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.

公开(公告)号：US20220244881A1

公开(公告)日：2022-08-04

申请号：US17248661

申请日：2021-02-02

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Mohamed Azimane

IPC: G06F3/06

Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.