公开(公告)号：US10685703B2

公开(公告)日：2020-06-16

申请号：US16129718

申请日：2018-09-12

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Sushikha Jain ,  Deepti Saini ,  Jwalant Kumar Mishra ,  Patrick Van de Steeg

IPC: G11C8/08 ,  G11C7/12 ,  G11C11/419 ,  G11C7/18 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11 ,  G11C5/14

Abstract: A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.

公开(公告)号：US20200082876A1

公开(公告)日：2020-03-12

申请号：US16129718

申请日：2018-09-12

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Sushikha Jain ,  Deepti Saini ,  Jwalant Kumar Mishra ,  Patrick Van de Steeg

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11 ,  G11C8/08 ,  G11C7/12 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.