公开(公告)号：US10679714B2

公开(公告)日：2020-06-09

申请号：US16399939

申请日：2019-04-30

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Jwalant Kumar Mishra ,  Patrick Van de Steeg

IPC: G11C8/08 ,  G11C17/08 ,  G11C11/412 ,  G11C11/417

Abstract: A read-only memory (ROM) includes ROM cells and a bias control circuit for biasing the ROM cells. Each ROM cell includes a set of transistors. The bias control circuit is connected to body terminals of the transistors of each ROM cell to provide a bias voltage. The bias voltage, which is temperature-dependent, is generated based on junction leakages at the body terminals of the transistors. The bias control circuit controls threshold voltages of the transistors using the bias voltage. The use of a temperature-dependent bias voltage to bias the body terminals of the transistors allows for a relatively constant read margin for each ROM cell.

公开(公告)号：US20200082894A1

公开(公告)日：2020-03-12

申请号：US16399939

申请日：2019-04-30

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Jwalant Kumar Mishra ,  Patrick Van de Steeg

IPC: G11C17/08 ,  G11C8/08 ,  G11C11/417 ,  G11C11/412

Abstract: A read-only memory (ROM) includes ROM cells and a bias control circuit for biasing the ROM cells. Each ROM cell includes a set of transistors. The bias control circuit is connected to body terminals of the transistors of each ROM cell to provide a bias voltage. The bias voltage, which is temperature-dependent, is generated based on junction leakages at the body terminals of the transistors. The bias control circuit controls threshold voltages of the transistors using the bias voltage. The use of a temperature-dependent bias voltage to bias the body terminals of the transistors allows for a relatively constant read margin for each ROM cell.

公开(公告)号：US20190080777A1

公开(公告)日：2019-03-14

申请号：US15700152

申请日：2017-09-10

Applicant: NXP B.V.

Inventor： Rajat Kohli ,  Patrick Van de Steeg ,  Jwalant Kumar Mishra ,  Pankaj Agarwal

IPC: G11C17/12 ,  G11C11/56 ,  G11C11/40

Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

公开(公告)号：US10685703B2

公开(公告)日：2020-06-16

申请号：US16129718

申请日：2018-09-12

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Sushikha Jain ,  Deepti Saini ,  Jwalant Kumar Mishra ,  Patrick Van de Steeg

IPC: G11C8/08 ,  G11C7/12 ,  G11C11/419 ,  G11C7/18 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11 ,  G11C5/14

Abstract: A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.

公开(公告)号：US20200082876A1

公开(公告)日：2020-03-12

申请号：US16129718

申请日：2018-09-12

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Sushikha Jain ,  Deepti Saini ,  Jwalant Kumar Mishra ,  Patrick Van de Steeg

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11 ,  G11C8/08 ,  G11C7/12 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.