公开(公告)号：US20160126169A1

公开(公告)日：2016-05-05

申请号：US14527302

申请日：2014-10-29

Applicant: NXP B.V.

Inventor： Chi Ho Leung ,  Yee Wai Fung ,  WaiKeung Ho

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, there is a leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. At least five I/O terminals each of said terminals comprise a respective metal side pad; and the respective metal side pad has a step profile. A feature of this embodiment is that these metal side pads, having a step profile, are electroplated to enhance their solderability.

Abstract translation: 与示例性实施例一致，存在无铅封装半导体器件，其具有顶部和底部相对的主表面和在其之间延伸的侧壁。 无引线封装半导体器件包括具有两个或更多个引线框架部分的阵列的引线框架子组件，每个引线框架部分均布置有半导体管芯。 每个所述端子中的至少五个I / O端子包括相应的金属侧焊盘; 并且相应的金属侧焊盘具有台阶轮廓。 该实施例的特征在于，具有阶梯轮廓的这些金属侧垫被电镀以增强其可焊性。

公开(公告)号：US09425130B2

公开(公告)日：2016-08-23

申请号：US14527365

申请日：2014-10-29

Applicant: NXP B.V.

Inventor： Chi Ho Leung ,  Wai Hung William Hor ,  Soenke Habenicht ,  Pompeo Umali ,  WaiKeung Ho ,  Yee Wai Fung

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. There are at least five I/O terminals wherein each of said terminals comprise a respective metal side pad wherein the respective metal side pad is disposed in a recess. A feature of this embodiment is that the each of the side pads is electroplated. The electroplated side pads accept solder and the solder menisci are contained by the recesses.

Abstract translation: 与示例性实施例一致，存在无铅封装半导体器件，其具有顶部和底部相对的主表面和在其之间延伸的侧壁。 无引线封装半导体器件包括具有两个或更多个引线框架部分的阵列的引线框架子组件，每个引线框架部分均布置有半导体管芯。 存在至少五个I / O端子，其中每个所述端子包括相应的金属侧焊盘，其中相应的金属侧焊盘设置在凹部中。 该实施例的特征在于每个侧垫都是电镀的。 电镀侧垫接受焊料，凹槽中容纳焊料半导体。

公开(公告)号：US20160126162A1

公开(公告)日：2016-05-05

申请号：US14527365

申请日：2014-10-29

Applicant: NXP B.V.

Inventor： Chi Ho Leung ,  Wai Hung William Hor ,  Soenke Habenicht ,  Pompeo Umali ,  WaiKeung Ho ,  Yee Wai Fung

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49537 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. There are at least five I/O terminals wherein each of said terminals comprise a respective metal side pad wherein the respective metal side pad is disposed in a recess. A feature of this embodiment is that the each of the side pads is electroplated. The electroplated side pads accept solder and the solder menisci are contained by the recesses.

Abstract translation: 与示例性实施例一致，存在无铅封装半导体器件，其具有顶部和底部相对的主表面和在其之间延伸的侧壁。 无引线封装半导体器件包括具有两个或更多个引线框架部分的阵列的引线框架子组件，每个引线框架部分均布置有半导体管芯。 存在至少五个I / O端子，其中每个所述端子包括相应的金属侧焊盘，其中相应的金属侧焊盘设置在凹部中。 该实施例的特征在于每个侧垫都是电镀的。 电镀侧垫接受焊料，凹槽中容纳焊料半导体。