公开(公告)号：US20220334181A1

公开(公告)日：2022-10-20

申请号：US17301936

申请日：2021-04-19

申请人： NXP USA, Inc.

发明人： Rohan Poudel ,  Anurag Jindal ,  Joseph Rollin Wright ,  Nipun Mahajan ,  Shruti Singla ,  Hemant Nautiyal

IPC分类号： G01R31/317 ,  G01R31/3193 ,  G01R31/3185

摘要： A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

公开(公告)号：US11513153B2

公开(公告)日：2022-11-29

申请号：US17301936

申请日：2021-04-19

申请人： NXP USA, Inc.

发明人： Rohan Poudel ,  Anurag Jindal ,  Joseph Rollin Wright ,  Nipun Mahajan ,  Shruti Singla ,  Hemant Nautiyal

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/3193

摘要： A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.