公开(公告)号：US20220334181A1

公开(公告)日：2022-10-20

申请号：US17301936

申请日：2021-04-19

申请人： NXP USA, Inc.

发明人： Rohan Poudel ,  Anurag Jindal ,  Joseph Rollin Wright ,  Nipun Mahajan ,  Shruti Singla ,  Hemant Nautiyal

IPC分类号： G01R31/317 ,  G01R31/3193 ,  G01R31/3185

摘要： A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

公开(公告)号：US11047904B2

公开(公告)日：2021-06-29

申请号：US16292654

申请日：2019-03-05

申请人： NXP USA, INC.

发明人： Kumar Abhishek ,  Srikanth Jagannathan ,  Thomas Henry Luedeke ,  Venkannababu Ambati ,  Mark Shelton Cinque ,  Joseph Rollin Wright

IPC分类号： G01R31/28

摘要： An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.

公开(公告)号：US11513153B2

公开(公告)日：2022-11-29

申请号：US17301936

申请日：2021-04-19

申请人： NXP USA, Inc.

发明人： Rohan Poudel ,  Anurag Jindal ,  Joseph Rollin Wright ,  Nipun Mahajan ,  Shruti Singla ,  Hemant Nautiyal

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/3193

摘要： A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.