公开(公告)号：US10892617B2

公开(公告)日：2021-01-12

申请号：US16368022

申请日：2019-03-28

申请人： NXP USA, Inc.

发明人： William E. Edwards ,  John M. Pigott

IPC分类号： H02H9/04 ,  H02H1/00 ,  H03K19/0175

摘要： An input protection circuit (200) and associated method are disclosed for protecting a circuit input (VINP) from positive and negative overvoltages at an input voltage (VIN) with a high-voltage PMOSFET (P1) having a gate, a drain connected across a zener diode (ZD1) to the gate, and a source connected to receive an input voltage; a blocking FET (N1) having a gate connected to a power supply voltage, a drain connected across a zener diode (ZD2) to the power supply voltage, and a source connected to the gate of the high-voltage PMOSFET; a high-voltage NMOSFET (N3) having a gate connected to the power supply voltage, a source providing the protected output voltage and connected across a zener diode (ZD3) to the gate, and a drain connected to a source follower node and a level shifter circuit (214) connected between the drain of the high-voltage PMOSFET and the source follower node.

公开(公告)号：US20200313425A1

公开(公告)日：2020-10-01

申请号：US16368022

申请日：2019-03-28

申请人： NXP USA, Inc.

发明人： William E. Edwards ,  John M. Pigott

IPC分类号： H02H9/04 ,  H03K19/0175 ,  H02H1/00

摘要： An input protection circuit (200) and associated method are disclosed for protecting a circuit input (VINP) from positive and negative overvoltages at an input voltage (VIN) with a high-voltage PMOSFET (P1) having a gate, a drain connected across a zener diode (ZD1) to the gate, and a source connected to receive an input voltage; a blocking FET (N1) having a gate connected to a power supply voltage, a drain connected across a zener diode (ZD2) to the power supply voltage, and a source connected to the gate of the high-voltage PMOSFET; a high-voltage NMOSFET (N3) having a gate connected to the power supply voltage, a source providing the protected output voltage and connected across a zener diode (ZD3) to the gate, and a drain connected to a source follower node and a level shifter circuit (214) connected between the drain of the high-voltage PMOSFET and the source follower node.

公开(公告)号：US10649033B2

公开(公告)日：2020-05-12

申请号：US15720057

申请日：2017-09-29

申请人： NXP USA, Inc.

发明人： William E. Edwards ,  Anthony F. Andresen ,  Randall C. Gray

IPC分类号： G01R31/02 ,  G01R31/327 ,  H03K17/18 ,  H02B1/24 ,  G01R19/165

摘要： The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.

公开(公告)号：US20180356466A1

公开(公告)日：2018-12-13

申请号：US16103349

申请日：2018-08-14

申请人： NXP USA, Inc.

发明人： William E. Edwards ,  Randall C. Gray ,  Anthony F. Andresen

IPC分类号： G01R31/327 ,  H03K17/18 ,  G01R19/165 ,  G01R31/02

CPC分类号： G01R31/3278 ,  G01R19/16571 ,  G01R31/025 ,  G01R31/3277 ,  H03K17/18 ,  H03K2217/0027

摘要： A circuit for diagnostic testing includes a current source coupled to a power source and configured to provide wetting current along a path to a load control switch, a current sensor connected in series with the current source along the path, the current sensor being configured to generate a current sensor signal indicative of a current level along the path, a voltage measurement unit having an input terminal coupled to a node along the path through which the wetting current flows to reach the load control switch, the voltage measurement unit being configured to detect a state of the load control switch based on a voltage at the node, and a controller coupled to the current sensor and the voltage measurement unit, the controller being configured to determine a wetting current diagnostic condition in accordance with the current level and the detected state.

公开(公告)号：US10101180B2

公开(公告)日：2018-10-16

申请号：US15655410

申请日：2017-07-20

申请人： NXP USA, Inc.

发明人： Mike R. Garrard ,  William E. Edwards

IPC分类号： F02P7/00 ,  G01D5/20 ,  F02P7/067 ,  F02P5/145 ,  G01B7/14 ,  F02P1/00

摘要： The embodiments described herein include systems with a variable reluctance sensor (VRS) interface and methods of their operation. Embodiments of VRS interfaces include a clearing signal generator configured to generate a clearing signal corresponding with the timing of a noise event. The clearing signal may be configured to clear a post-processing circuit.