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6 条记录 (耗时 0.157 秒)

    A Method and Apparatus for Reducing Leakage in Integrated Circuits
    1.
    发明申请
    A Method and Apparatus for Reducing Leakage in Integrated Circuits 有权
    一种降低集成电路泄漏的方法和装置

    公开(公告)号：US20070007996A1

    公开(公告)日：2007-01-11

    申请号：US11422973

    申请日：2006-06-08

    申请人： Nagarajan Ranganathan ,  Narender Hanchate

    发明人： Nagarajan Ranganathan ,  Narender Hanchate

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00361 ,  H03K17/162 ,  H03K17/6872 ,  H03K19/0013 ,  H03K2217/0036

    摘要： An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.

    摘要翻译： 描述了根据本发明的有效设计方法，用于减少CMOS电路中的泄漏功率。 根据本发明的方法和装置随着阈值电压的降低而产生更好的泄漏减少，从而有助于进一步降低电源电压并最小化晶体管尺寸。 与其他泄漏控制技术不同，本发明的技术不需要任何控制电路来监测电路的状态。 因此，避免以附加电路消耗的动态功率的形式牺牲获得的泄漏功率降低以控制整体电路状态。

    Method and apparatus for reducing leakage in integrated circuits
    2.
    发明授权
    Method and apparatus for reducing leakage in integrated circuits 有权
    降低集成电路泄漏的方法和装置

    公开(公告)号：US07256608B2

    公开(公告)日：2007-08-14

    申请号：US11422973

    申请日：2006-06-08

    申请人： Nagarajan Ranganathan ,  Narender Hanchate

    发明人： Nagarajan Ranganathan ,  Narender Hanchate

    IPC分类号： H03K17/16

    CPC分类号： H03K19/00361 ,  H03K17/162 ,  H03K17/6872 ,  H03K19/0013 ,  H03K2217/0036

    摘要： An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.

    摘要翻译： 描述了根据本发明的有效设计方法，用于减少CMOS电路中的泄漏功率。 根据本发明的方法和装置随着阈值电压的降低而产生更好的泄漏减少，从而有助于进一步降低电源电压并最小化晶体管尺寸。 与其他泄漏控制技术不同，本发明的技术不需要任何控制电路来监测电路的状态。 因此，避免以附加电路消耗的动态功率的形式牺牲获得的泄漏功率降低以控制整体电路状态。

    INTEGRATED SINGLE SPICE DECK SENSITIZATION FOR GATE LEVEL TOOLS
    3.
    发明申请
    INTEGRATED SINGLE SPICE DECK SENSITIZATION FOR GATE LEVEL TOOLS 有权
    针对门级水平工具的集成单个单位敏感度

    公开(公告)号：US20100005429A1

    公开(公告)日：2010-01-07

    申请号：US12166630

    申请日：2008-07-02

    申请人： Jindrich Zejda ,  Narender Hanchate ,  Rupesh Nayak ,  Li Ding

    发明人： Jindrich Zejda ,  Narender Hanchate ,  Rupesh Nayak ,  Li Ding

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/505

    摘要： One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.

    摘要翻译： 本发明的一个实施例提供了用于产生子电路的晶体管级描述的系统和技术。 用户可能需要使用晶体管级模拟器来模拟电路中的分支电路，并且子电路中的一个或多个单元可能需要被敏化，使得当模拟子电路时，单元格处于期望状态。 实施例通过将模拟开关插入需要敏化的单元前面来修改子电路，使得模拟开关可用于在晶体管级仿真期间向单元施加致敏序列。 然后，该实施例可以生成修改后的子电路的晶体管级描述。 接下来，可以存储子电路的晶体管级描述，从而使晶体管级模拟器能够模拟子电路。

    Integrated single spice deck sensitization for gate level tools
    6.
    发明授权
    Integrated single spice deck sensitization for gate level tools 有权
    综合单一香料甲板敏化门级工具

    公开(公告)号：US08091049B2

    公开(公告)日：2012-01-03

    申请号：US12166630

    申请日：2008-07-02

    申请人： Jindrich Zejda ,  Narender Hanchate ,  Rupesh Nayak ,  Li Ding

    发明人： Jindrich Zejda ,  Narender Hanchate ,  Rupesh Nayak ,  Li Ding

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/505

    摘要： One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.

    摘要翻译： 本发明的一个实施例提供了用于产生子电路的晶体管级描述的系统和技术。 用户可能需要使用晶体管级模拟器来模拟电路中的分支电路，并且子电路中的一个或多个单元可能需要被敏化，使得当模拟子电路时，单元格处于期望状态。 实施例通过将模拟开关插入需要敏化的单元前面来修改子电路，使得模拟开关可用于在晶体管级仿真期间向单元施加致敏序列。 然后，该实施例可以生成修改后的子电路的晶体管级描述。 接下来，可以存储子电路的晶体管级描述，从而使晶体管级模拟器能够模拟子电路。