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公开(公告)号：US08112621B2
公开(公告)日：2012-02-07
申请号：US12526624
申请日：2009-04-23
IPC分类号： G06F12/06
CPC分类号： G06F12/109 , G06F3/06
摘要： Even if each processor core uses the same logical address, a processing-target program corresponding to each processor core can be selected. A logical address of multiple address mapping tables is set to a same logical address in correspondence with an embedded OS program or a RAID management program, and a physical address is set to a different physical address in correspondence with the actual storage destination of an embedded OS program or a RAID management program. Each processor core, on start-up, uses a self address mapping table to execute address mapping processing with each processor core based on the same logical address, selects an embedded OS program or a RAID management program according to the physical address obtained in the address mapping processing, and executes processing according to the selected program.
摘要翻译： 即使每个处理器核心使用相同的逻辑地址，也可以选择与每个处理器核心对应的处理目标程序。 将多个地址映射表的逻辑地址设置为与嵌入式OS程序或RAID管理程序相对应的相同逻辑地址，并且物理地址被设置为与嵌入式OS的实际存储目的地相对应的不同物理地址 程序或RAID管理程序。 每个处理器核心在启动时使用自地址映射表，以基于同一逻辑地址的每个处理器核心执行地址映射处理，根据地址中获得的物理地址选择嵌入式OS程序或RAID管理程序 映射处理，并根据所选择的程序执行处理。
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2.发明申请公开(公告)号：US20110138160A1
公开(公告)日：2011-06-09
申请号：US12526624
申请日：2009-04-23
CPC分类号： G06F12/109 , G06F3/06
摘要： Even if each processor core uses the same logical address, a processing-target program corresponding to each processor core can be selected. A logical address of multiple address mapping tables is set to a same logical address in correspondence with an embedded OS program or a RAID management program, and a physical address is set to a different physical address in correspondence with the actual storage destination of an embedded OS program or a RAID management program. Each processor core, on start-up, uses a self address mapping table to execute address mapping processing with each processor core based on the same logical address, selects an embedded OS program or a RAID management program according to the physical address obtained in the address mapping processing, and executes processing according to the selected program.
摘要翻译： 即使每个处理器核心使用相同的逻辑地址，也可以选择与每个处理器核心对应的处理目标程序。 将多个地址映射表的逻辑地址设置为与嵌入式OS程序或RAID管理程序相对应的相同逻辑地址，并且物理地址被设置为与嵌入式OS的实际存储目的地相对应的不同物理地址 程序或RAID管理程序。 每个处理器核心在启动时使用自地址映射表，以基于同一逻辑地址的每个处理器核心执行地址映射处理，根据地址中获得的物理地址选择嵌入式OS程序或RAID管理程序 映射处理，并根据所选择的程序执行处理。
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公开(公告)号：US20070209037A1
公开(公告)日：2007-09-06
申请号：US11407972
申请日：2006-04-21
申请人： Nakaba Sato , Toshiaki Terao , Hiroji Shibuya
发明人： Nakaba Sato , Toshiaki Terao , Hiroji Shibuya
IPC分类号： G06F9/46
CPC分类号： G06F9/4812 , G06F9/4881
摘要： A storage system has a single processor that operates in a multitasking operating system environment. An operation time manager adjusts the balance between processing time proportions for interrupt processing and task processing requested of the storage system internally and externally so that those processing time proportions become within respective predetermined ranges.
摘要翻译： 存储系统具有在多任务操作系统环境中操作的单个处理器。 操作时间管理器在内部和外部调整中断处理和存储系统所请求的任务处理的处理时间比例之间的平衡，使得那些处理时间比例成为相应的预定范围。
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4.发明授权System for monitoring time proportion for interrupt or task processing with restriction placed in subsequent monitoring time period when allowable time proportion is exceed 有权用于监视中断或任务处理的时间比例的系统，限制在允许时间比例超过的后续监视时间段内公开(公告)号：US07950013B2
公开(公告)日：2011-05-24
申请号：US11407972
申请日：2006-04-21
申请人： Nakaba Sato , Toshiaki Terao , Hiroji Shibuya
发明人： Nakaba Sato , Toshiaki Terao , Hiroji Shibuya
CPC分类号： G06F9/4812 , G06F9/4881
摘要： A storage system has a single processor that operates in a multitasking operating system environment. An operation time manager adjusts the balance between processing time proportions for interrupt processing and task processing requested of the storage system internally and externally so that those processing time proportions become within respective predetermined ranges.
摘要翻译： 存储系统具有在多任务操作系统环境中操作的单个处理器。 操作时间管理器在内部和外部调整中断处理和存储系统所请求的任务处理的处理时间比例之间的平衡，使得那些处理时间比例成为相应的预定范围。
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公开(公告)号：US20130111270A1
公开(公告)日：2013-05-02
申请号：US13319882
申请日：2011-10-26
申请人： Toshio Kimura , Jun Kitahara , Hiroji Shibuya , Kazushige Nagamatsu , Nakaba Sato , Mika Teranishi
发明人： Toshio Kimura , Jun Kitahara , Hiroji Shibuya , Kazushige Nagamatsu , Nakaba Sato , Mika Teranishi
IPC分类号： G06F11/28
CPC分类号： G06F11/3632 , G06F11/3664
摘要： The present invention enables program codes to be shared among processors 211. To prevent the debug operation of one processor 211 from affecting the debug operation of the other processors 211, when detecting a breakpoint during execution of a program code, a debugger 410 or a debugger stub 520 controls the execution of the program code while exchanging breakpoint information 800 with the other debuggers 410 or the other debugger stubs 520. Furthermore, a circuit 170 is created which prevents the program code being carelessly rewritten due to thermal runaway, a bug, and the like of a processor 211, and the protection setting by the protection logic 71 in the circuit 170 is released only in case the processor 211 accesses each of a plurality of registers from 65 to 67 in specified order.
摘要翻译： 本发明使得能够在处理器211之间共享程序代码。为了防止一个处理器211的调试操作影响其他处理器211的调试操作，当在执行程序代码期间检测到断点时，调试器410或调试器 存根520控制程序代码的执行，同时与其他调试器410或其他调试器存根520交换断点信息800.此外，创建电路170，防止程序代码由于热失控，错误和 只有在处理器211以规定的顺序从65到67访问多个寄存器中的每一个的情况下才释放处理器211的保护逻辑71的保护设置。
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6.发明授权公开(公告)号：US08874965B2
公开(公告)日：2014-10-28
申请号：US13319882
申请日：2011-10-26
申请人： Toshio Kimura , Jun Kitahara , Hiroji Shibuya , Kazushige Nagamatsu , Nakaba Sato , Mika Teranishi
发明人： Toshio Kimura , Jun Kitahara , Hiroji Shibuya , Kazushige Nagamatsu , Nakaba Sato , Mika Teranishi
CPC分类号： G06F11/3632 , G06F11/3664
摘要： The present invention enables program codes to be shared among processors 211. To prevent the debug operation of one processor 211 from affecting the debug operation of the other processors 211, when detecting a breakpoint during execution of a program code, a debugger 410 or a debugger stub 520 controls the execution of the program code while exchanging breakpoint information 800 with the other debuggers 410 or the other debugger stubs 520. Furthermore, a circuit 170 is created which prevents the program code being carelessly rewritten due to thermal runaway, a bug, and the like of a processor 211, and the protection setting by the protection logic 71 in the circuit 170 is released only in case the processor 211 accesses each of a plurality of registers from 65 to 67 in specified order.
摘要翻译： 本发明使得能够在处理器211之间共享程序代码。为了防止一个处理器211的调试操作影响其他处理器211的调试操作，当在执行程序代码期间检测到断点时，调试器410或调试器 存根520控制程序代码的执行，同时与其他调试器410或其他调试器存根520交换断点信息800.此外，创建电路170，防止程序代码由于热失控，错误和 只有在处理器211以规定的顺序从65到67访问多个寄存器中的每一个的情况下才释放处理器211的保护逻辑71的保护设置。
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