公开(公告)号：US07561481B2

公开(公告)日：2009-07-14

申请号：US11760955

申请日：2007-06-11

申请人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

发明人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

IPC分类号： G11C7/00

CPC分类号： G06F13/1694

摘要： Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

摘要翻译： 提供了存储器控制器及其优化焊盘序列的方法。 首先提供用于至少一个存储器件的印刷电路板上的至少两个不同的优选迹线序列。 然后提供一个存储器控制器以具有核心逻辑电路，多个输入/输出（I / O）设备和重新启动器。 核心逻辑有I / O端子。 单个芯片上的每个I / O设备都有一个焊盘。 重排器耦合在核心逻辑电路和输入/输出设备之间，可编程以将输入/输出设备选择性地连接到输入/输出端子。 后续程序随后被编程为选择并将输入/输出设备的一部分连接到输入/输出端子，使得基本上支持不同优选轨迹序列之一。

公开(公告)号：US20080304352A1

公开(公告)日：2008-12-11

申请号：US11760955

申请日：2007-06-11

申请人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

发明人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

IPC分类号： G11C8/06

CPC分类号： G06F13/1694

摘要： Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

摘要翻译： 提供了存储器控制器及其优化焊盘序列的方法。 首先提供用于至少一个存储器件的印刷电路板上的至少两个不同的优选迹线序列。 然后提供一个存储器控制器以具有核心逻辑电路，多个输入/输出（I / O）设备和重新启动器。 核心逻辑有I / O端子。 单个芯片上的每个I / O设备都有一个焊盘。 重排器耦合在核心逻辑电路和输入/输出设备之间，可编程以将输入/输出设备选择性地连接到输入/输出端子。 后续程序随后被编程为选择并将输入/输出设备的一部分连接到输入/输出端子，使得基本上支持不同优选轨迹序列之一。