公开(公告)号：US07142470B2

公开(公告)日：2006-11-28

申请号：US11086553

申请日：2005-03-22

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. A divided frequency signal is generated by dividing a frequency of the internal clock. A phase of the divided frequency signal is adjusted according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal. Finally, the latch clock is generated according to the delay parameter and the internal clock.

摘要翻译： 用于在存储器读数中产生锁存时钟的方法和系统。 具有第一逻辑电平和第二逻辑电平的数据分别存储到存储器的第一地址和第二地址中。 通过发出用于在存储器的第一和第二地址重复检索数据的连续读取命令来产生读取数据信号。 通过分频内部时钟的频率来产生分频信号。 通过改变延迟参数，根据延迟参数来调整分频信号的相位，直到划分的频率信号的至少边缘与读数据信号的任何边缘对齐。 最后，根据延迟参数和内部时钟产生锁存时钟。

公开(公告)号：US20070041253A1

公开(公告)日：2007-02-22

申请号：US11551771

申请日：2006-10-23

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. Varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned. Finally, the latch clock is generated according to the delay parameter and the internal clock.

摘要翻译： 用于在存储器读数中产生锁存时钟的方法和系统。 具有第一逻辑电平和第二逻辑电平的数据分别存储到存储器的第一地址和第二地址中。 通过发出用于在存储器的第一和第二地址重复检索数据的连续读取命令来产生读取数据信号。 改变延迟参数，直到内部时钟信号的至少边缘和读取数据信号的任何边缘对齐。 最后，根据延迟参数和内部时钟产生锁存时钟。

公开(公告)号：US07876629B2

公开(公告)日：2011-01-25

申请号：US11835422

申请日：2007-08-08

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C2207/2254

摘要： A memory control method for adjusting sampling points utilized by a memory control circuit receiving a data signal and an original data strobe signal of a memory includes: utilizing at least one delay unit to provide a plurality of sampling points according to the original data strobe signal; sampling according to the data signal by utilizing the plurality of sampling points; and analyzing sampling results to dynamically determine a delay amount for delaying the original data strobe signal, whereby a sampling point corresponding to the delayed data strobe signal is kept centered at data carried by the data signal.

摘要翻译： 一种存储器控制方法，用于调整接收数据信号的存储器控​​制电路和存储器的原始数据选通信号所使用的采样点，包括：利用至少一个延迟单元根据原始数据选通信号提供多个采样点; 利用多个采样点根据数据信号进行采样; 并且分析采样结果以动态地确定用于延迟原始数据选通信号的延迟量，由此对应于延迟的数据选通信号的采样点以数据信号携带的数据为中心。

公开(公告)号：US07652938B2

公开(公告)日：2010-01-26

申请号：US11551771

申请日：2006-10-23

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. Varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned. Finally, the latch clock is generated according to the delay parameter and the internal clock.

摘要翻译： 用于在存储器读数中产生锁存时钟的方法和系统。 具有第一逻辑电平和第二逻辑电平的数据分别存储到存储器的第一地址和第二地址中。 通过发出用于在存储器的第一和第二地址重复检索数据的连续读取命令来产生读取数据信号。 改变延迟参数，直到内部时钟信号的至少边缘和读取数据信号的任何边缘对齐。 最后，根据延迟参数和内部时钟产生锁存时钟。

公开(公告)号：US20090043953A1

公开(公告)日：2009-02-12

申请号：US11835422

申请日：2007-08-08

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： G06F12/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C2207/2254

摘要： A memory control method for adjusting sampling points utilized by a memory control circuit receiving a data signal and an original data strobe signal of a memory includes: utilizing at least one delay unit to provide a plurality of sampling points according to the original data strobe signal; sampling according to the data signal by utilizing the plurality of sampling points; and analyzing sampling results to dynamically determine a delay amount for delaying the original data strobe signal, whereby a sampling point corresponding to the delayed data strobe signal is kept centered at data carried by the data signal.

摘要翻译： 一种存储器控制方法，用于调整接收数据信号的存储器控​​制电路和存储器的原始数据选通信号所使用的采样点，包括：利用至少一个延迟单元根据原始数据选通信号提供多个采样点; 利用多个采样点根据数据信号进行采样; 并且分析采样结果以动态地确定用于延迟原始数据选通信号的延迟量，由此对应于延迟的数据选通信号的采样点以数据信号携带的数据为中心。

公开(公告)号：US07362107B2

公开(公告)日：2008-04-22

申请号：US11164029

申请日：2005-11-08

申请人： Jui-Hsing Tseng ,  Yu-Ping Ho

发明人： Jui-Hsing Tseng ,  Yu-Ping Ho

IPC分类号： G01R35/00

CPC分类号： G11C29/02 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03L7/0814

摘要： A calibrating system for automatically eliminating or reducing imbalance between a first signal and a second signal is disclosed. The calibrating system includes: a programmable delay module, receiving to the first and the second signals; a phase detecting module, coupled to the programmable delay module, for receiving the first and the second signals from the programmable delay module, and comparing a phase of a reference signal with phases of the first and the second signals, respectively; and a de-skew controlling module, coupled to the programmable delay module and the phase detecting module, for controlling the programmable delay module to eliminate imbalance between the first and the second signals by at least delaying the first signal according to a comparison result of the phase detecting module.

摘要翻译： 公开了一种用于自动消除或减少第一信号和第二信号之间的不平衡的校准系统。 校准系统包括：可编程延迟模块，接收第一和第二信号; 相位检测模块，耦合到所述可编程延迟模块，用于从所述可编程延迟模块接收所述第一和第二信号，并将参考信号的相位分别与所述第一和第二信号的相位进行比较; 以及耦合到所述可编程延迟模块和所述相位检测模块的去偏移控制模块，用于通过至少延迟所述第一信号的比较结果来控制所述可编程延迟模块以消除所述第一和第二信号之间的不平衡， 相位检测模块。

公开(公告)号：US07236027B2

公开(公告)日：2007-06-26

申请号：US11463897

申请日：2006-08-11

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： H03L7/06

CPC分类号： H03L7/085 ,  H03L7/0814

摘要： A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit and the reference clock for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.

摘要翻译： 延迟锁定环路延迟锁定延迟时钟的参考时钟。 延迟锁定环路电路包括用于将基准时钟的频率除以N的时钟分频器，以产生分频时钟;电连接到时钟分频器的可编程延迟电路，用于延迟分频时钟以产生延迟的时钟; 电耦合到可编程延迟电路的180°相位检测器和用于检测延迟时钟的相位变化的参考时钟，以及电耦合到可编程延迟电路的延迟锁定环控制器和用于对可编程延迟进行编程的180°相位检测器 电路根据相位变化锁定延迟时钟。

公开(公告)号：US20060215466A1

公开(公告)日：2006-09-28

申请号：US11086553

申请日：2005-03-22

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. A divided frequency signal is generated by dividing a frequency of the internal clock. A phase of the divided frequency signal is adjusted according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal. Finally, the latch clock is generated according to the delay parameter and the internal clock.

公开(公告)号：US20060055440A1

公开(公告)日：2006-03-16

申请号：US10711313

申请日：2004-09-10

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： H03L7/06

CPC分类号： H03L7/085 ,  H03L7/0814

摘要： A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.

摘要翻译： 延迟锁定环路延迟锁定延迟时钟的参考时钟。 延迟锁定环路电路包括用于将基准时钟的频率除以N的时钟分频器，以产生分频时钟;电连接到时钟分频器的可编程延迟电路，用于延迟分频时钟以产生延迟的时钟; 电耦合到可编程延迟电路的180°相位检测器，用于检测延迟时钟的相位变化;以及延迟锁定环控制器，其电耦合到可编程延迟电路和180°相位检测器，用于编程可编程延迟电路以锁定 延迟时钟根据相位变化。

公开(公告)号：US07778093B2

公开(公告)日：2010-08-17

申请号：US11835423

申请日：2007-08-08

申请人： Jui-Hsing Tseng

发明人： Jui-Hsing Tseng

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： A memory control method for adjusting deglitch windows utilized by a memory control circuit receiving an original data strobe signal of a memory includes: deglitching according to the original data strobe signal by utilizing a plurality of deglitch windows that are set by delaying an original deglitch window signal in order to derive a plurality of deglitch results, where the deglitch windows have different beginning time points; and utilizing the deglitch results to dynamically determine a delay amount for delaying the original deglitch window signal, where the beginning time point of one of the deglitch windows is kept centered at a middle time point of a preamble of the original data strobe signal.

摘要翻译： 一种存储器控制方法，用于调整接收存储器的原始数据选通信号的存储器控​​制电路所使用的去视窗，包括：通过利用通过延迟原始反纹迹窗口信号而设置的多个反纹差窗口，根据原始数据选通信号进行减光 为了导出多个反切割结果，其中消隐窗口具有不同的开始时间点; 并且利用deglitch结果来动态地确定延迟原始deglitch窗口信号的延迟量，其中一个消隐窗口的开始时间点保持在原始数据选通信号的前同步码的中间时间点的中心。