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    Nonvolatile semiconductor memory and a fabrication method for the same
    1.
    发明授权
    Nonvolatile semiconductor memory and a fabrication method for the same 失效
    非易失性半导体存储器及其制造方法

    公开(公告)号：US07268386B2

    公开(公告)日：2007-09-11

    申请号：US10983058

    申请日：2004-11-08

    申请人： Naohisa Iino ,  Atsushi Murakawa

    发明人： Naohisa Iino ,  Atsushi Murakawa

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

    摘要： A nonvolatile semiconductor memory including: a plurality of stripe-shaped active regions extending in a bit line direction; device isolation regions having tops arranged at a location higher than the active regions; a plurality of word lines and select gate lines intersecting with the bit line direction; and memory cell transistors arranged at the intersections of the active regions and the word lines via gate insulator films, including floating gate electrodes formed on the device isolation regions and gate insulator films on the active regions, and isolated on the device isolation regions, control gate electrodes arranged on the floating gate electrodes, and inter-gate insulator films arranged between the control gate electrodes and the floating gate electrodes; wherein, the thickness of the floating gate electrodes on the active regions and a maximum thickness of the floating gate electrodes on the device isolation regions are substantially the same, and steps are provided at the edges of the floating gate electrodes isolated on the device isolation regions.

    摘要翻译： 一种非易失性半导体存储器，包括：沿位线方向延伸的多个条状有源区域; 器件隔离区域，其顶部布置在高于有源区域的位置; 多个字线和与位线方向相交的选择栅极线; 以及存储单元晶体管，其经由栅极绝缘体膜布置在有源区和字线的交点处，包括形成在器件隔离区上的浮栅和有源区上的栅极绝缘膜，并且在器件隔离区上分离控制栅 布置在浮栅电极上的电极和布置在控制栅电极和浮栅之间的栅间绝缘膜; 其中，有源区上的浮置栅电极的厚度和器件隔离区上的浮置栅电极的最大厚度基本上相同，并且在器件隔离区隔开的浮栅电极的边缘设置步骤 。

    Nonvolatile semiconductor memory and a fabrication method for the same
    2.
    发明申请
    Nonvolatile semiconductor memory and a fabrication method for the same 失效
    非易失性半导体存储器及其制造方法

    公开(公告)号：US20050224862A1

    公开(公告)日：2005-10-13

    申请号：US10983058

    申请日：2004-11-08

    申请人： Naohisa Iino ,  Atsushi Murakawa

    发明人： Naohisa Iino ,  Atsushi Murakawa

    IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

    摘要： A nonvolatile semiconductor memory including: a plurality of stripe-shaped active regions extending in a bit line direction; device isolation regions having tops arranged at a location higher than the active regions; a plurality of word lines and select gate lines intersecting with the bit line direction; and memory cell transistors arranged at the intersections of the active regions and the word lines via gate insulator films, including floating gate electrodes formed on the device isolation regions and gate insulator films on the active regions, and isolated on the device isolation regions, control gate electrodes arranged on the floating gate electrodes, and inter-gate insulator films arranged between the control gate electrodes and the floating gate electrodes; wherein, the thickness of the floating gate electrodes on the active regions and a maximum thickness of the floating gate electrodes on the device isolation regions are substantially the same, and steps are provided at the edges of the floating gate electrodes isolated on the device isolation regions.

    摘要翻译： 一种非易失性半导体存储器，包括：沿位线方向延伸的多个条状有源区域; 器件隔离区域，其顶部布置在高于有源区域的位置; 多个字线和与位线方向相交的选择栅极线; 以及存储单元晶体管，其经由栅极绝缘体膜布置在有源区和字线的交点处，包括形成在器件隔离区上的浮栅和有源区上的栅极绝缘膜，并且在器件隔离区上分离控制栅 布置在浮栅电极上的电极和布置在控制栅电极和浮栅之间的栅间绝缘膜; 其中，有源区上的浮置栅电极的厚度和器件隔离区上的浮置栅电极的最大厚度基本上相同，并且在器件隔离区隔开的浮栅电极的边缘设置步骤 。